公开(公告)号：US20250089345A1

公开(公告)日：2025-03-13

申请号：US18824088

申请日：2024-09-04

Applicant: Applied Materials, Inc.

Inventor： San-Kuei Lin ,  Pradeep K. Subrahmanyan

IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular, and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers that are protected from material loss during removal of a middle sacrificial layer. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a middle sacrificial layer on a top surface of the first hGAA structure, the middle sacrificial layer comprising silicon germanium (SiGe); and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise silicon germanium (SiGe). The middle sacrificial layer and the nanosheet release layers can comprise silicon germanium (SiGe) having the same or substantially the same geranium content.

公开(公告)号：US20250056871A1

公开(公告)日：2025-02-13

申请号：US18933127

申请日：2024-10-31

Applicant: Applied Materials, Inc.

Inventor： San-Kuei Lin ,  Pradeep K. Subrahmanyan

IPC: H01L21/8238 ,  H01L21/768 ,  H01L29/15 ,  H01L29/66

Abstract: Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.

公开(公告)号：US20250089355A1

公开(公告)日：2025-03-13

申请号：US18824195

申请日：2024-09-04

Applicant: Applied Materials, Inc.

Inventor： San-Kuei Lin ,  Pradeep K. Subrahmanyan

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. Some embodiments of the methods include conventional dipole engineering techniques such as dipole first processes and/or dipole last processes without the need for repairing the interfacial layer after treatment (in dipole first processes) or repairing the high-κ dielectric layer after the annealing process (in dipole last processes).

公开(公告)号：US20240055269A1

公开(公告)日：2024-02-15

申请号：US17886285

申请日：2022-08-11

Applicant: Applied Materials, Inc.

Inventor： Sankuei Lin ,  Changwoo Sun ,  Pradeep K. Subrahmanyan

IPC: H01L21/311 ,  H01L27/115

CPC classification number: H01L21/31116 ,  H01L27/115 ,  H01L21/31144

Abstract: A three-dimensional (3D) NAND memory structure may include alternating layers of materials arranged in a vertical stack on a silicon substrate, such as alternating oxide and nitride layers. The alternating nitride layers may later be removed, and the recesses may be filled with a conductive material to form word lines for the memory array. To avoid pinching off these recesses with silicon byproducts from a traditional wet etch, a dry etch may be instead be used to remove the nitrite layers. To protect the silicon substrate, a first insulating layer may be deposited at the bottom of the slit to cover the exposed silicon substrate before performing the dry etch. After applying a second insulating layer to cover the alternating oxide/nitride layers, a directional etch may punch through both insulating layers to again expose the silicon substrate before applying a solid material fill in the slit.

公开(公告)号：US20230037719A1

公开(公告)日：2023-02-09

申请号：US17531726

申请日：2021-11-20

Applicant: Applied Materials, Inc.

Inventor： SanKuei Lin ,  Pradeep K. Subrahmanyan

IPC: H01L21/8238 ,  H01L29/66

Abstract: Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.

公开(公告)号：US12170230B2

公开(公告)日：2024-12-17

申请号：US17531726

申请日：2021-11-20

Applicant: Applied Materials, Inc.

Inventor： SanKuei Lin ,  Pradeep K. Subrahmanyan

IPC: H01L21/76 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/768 ,  H01L29/15

Abstract: Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.

公开(公告)号：US20240268108A1

公开(公告)日：2024-08-08

申请号：US18634306

申请日：2024-04-12

Applicant: Applied Materials, Inc.

Inventor： Yong Yang ,  Jacqueline S. Wrench ,  Yixiong Yang ,  Pradeep K. Subrahmanyan ,  Srinivas Gandikota

IPC: H10B41/27 ,  G11C5/06 ,  H01L21/8234 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L21/823437 ,  H01L21/823462 ,  H10B43/27

Abstract: A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.

公开(公告)号：US20220384469A1

公开(公告)日：2022-12-01

申请号：US17329484

申请日：2021-05-25

Applicant: Applied Materials, Inc.

Inventor： Yong Yang ,  Jacqueline S. Wrench ,  Yixiong Yang ,  Pradeep K. Subrahmanyan ,  Srinivas Gandikota

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L21/8234

Abstract: A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.

公开(公告)号：US11997849B2

公开(公告)日：2024-05-28

申请号：US17329484

申请日：2021-05-25

Applicant: Applied Materials, Inc.

Inventor： Yong Yang ,  Jacqueline S. Wrench ,  Yixiong Yang ,  Pradeep K. Subrahmanyan ,  Srinivas Gandikota

IPC: H10B41/27 ,  G11C5/06 ,  H01L21/8234 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L21/823437 ,  H01L21/823462 ,  H10B43/27

Abstract: A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.

公开(公告)号：US20240046966A1

公开(公告)日：2024-02-08

申请号：US18366903

申请日：2023-08-08

Applicant: Applied Materials, Inc.

Inventor： Hsiang Yu Lee ,  Pradeep K. Subrahmanyan ,  Takaya Matsushita ,  Changwoo Sun

IPC: G11C5/06 ,  H10B43/20 ,  H10B43/35

CPC classification number: G11C5/063 ,  H10B43/20 ,  H10B43/35

Abstract: A three-dimensional (3D) NAND memory structure may include material layers arranged in a vertical stack including alternating horizontal insulating layers and wordline layers. The material layers may be etched to form a landing pad. A vertical wordline may extend through one or more of the horizontal wordline layers beneath the landing pad. The vertical wordline may be conductively connected to a top horizontal wordline, and the vertical wordline may be insulated from any of the horizontal wordlines that the vertical wordline extends through beneath the top horizontal wordline. A liner may also be formed over a top horizontal wordline at the landing pad.