Invention Grant
- Patent Title: Conductive route patterning for electronic substrates
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Application No.: US17026703Application Date: 2020-09-21
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Publication No.: US12027466B2Publication Date: 2024-07-02
- Inventor: Jeremy D. Ecton , Aleksandar Aleksov , Brandon C. Marin , Yonggang Li , Leonel Arana , Suddhasattwa Nad , Haobo Chen , Tarek Ibrahim
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/768 ; H05K1/11

Abstract:
Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.
Public/Granted literature
- US20220093520A1 CONDUCTIVE ROUTE PATTERNING FOR ELECTRONIC SUBSTRATES Public/Granted day:2022-03-24
Information query
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