公开(公告)号：US11605867B2

公开(公告)日：2023-03-14

申请号：US17344715

申请日：2021-06-10

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Jeremy D. Ecton ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Yonggang Li ,  Dilan Seneviratne

IPC分类号： H01P1/208 ,  H01P1/20 ,  H01P7/10 ,  H01L23/66 ,  H01P3/16 ,  H01L21/768 ,  H01P11/00 ,  H01L21/288

摘要： A method of fabricating an RF filter on a semiconductor package comprises forming a first dielectric buildup film. A second dielectric buildup film is formed over the first dielectric buildup film, the second dielectric buildup film comprising a dielectric material that contains a metallization catalyst, wherein the dielectric material comprises one of an epoxy-polymer blend dielectric material, silicon dioxide and silicon nitride, and a low-k dielectric. A trench is formed in the second dielectric buildup film with laser ablation, wherein the laser ablation selectively activates sidewalls of the trench for electroless metal deposition. A metal selectively is plated to sidewalls of the trench based at least in part on the metallization catalyst and immersion in an electroless solution. A low-loss buildup film is formed over the metal that substantially fills the trench.

公开(公告)号：US20220093520A1

公开(公告)日：2022-03-24

申请号：US17026703

申请日：2020-09-21

申请人： Intel Corporation

发明人： Jeremy D. Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Yonggang Li ,  Leonel Arana ,  Suddhasattwa Nad ,  Haobo Chen ,  Tarek Ibrahim

IPC分类号： H01L23/538 ,  H05K1/11 ,  H01L21/768

摘要： Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

公开(公告)号：US10290557B2

公开(公告)日：2019-05-14

申请号：US15549970

申请日：2015-03-09

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Trina Ghosh Dastidar ,  Dilan Seneviratne ,  Yonggang Li ,  Sirisha Chava

IPC分类号： H05K3/10 ,  H01L23/14 ,  H05K3/06 ,  H05K3/18 ,  H01L23/498 ,  H01L21/48

摘要： Embodiments of the present disclosure describe selective metallization of an integrated circuit (IC) substrate. In one embodiment, an integrated circuit (IC) substrate may include a dielectric material and metal crystals having a polyhedral shape dispersed in the dielectric material and bonded with a ligand that is to ablate when exposed to laser light such that the metal crystals having the ablated ligand are activated to provide a catalyst for selective electroless deposition of a metal. Other embodiments may be described and/or claimed.

公开(公告)号：US09716084B2

公开(公告)日：2017-07-25

申请号：US15208502

申请日：2016-07-12

申请人： INTEL CORPORATION

发明人： Digvijay A. Raorane ,  Yonggang Li ,  Rahul N. Manepalli ,  Javier Soto Gonzalez

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L21/683 ,  H01L23/522 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

CPC分类号： H01L25/50 ,  H01L21/4846 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/8385 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/40501 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00 ,  H01L2924/014

摘要： Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20150171067A1

公开(公告)日：2015-06-18

申请号：US14636016

申请日：2015-03-02

申请人： INTEL CORPORATION

发明人： Digvijay A. Raorane ,  Yonggang Li ,  Rahul N. Manepalli ,  Javier Soto Gonzalez

IPC分类号： H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L21/4846 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/8385 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/40501 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00 ,  H01L2924/014

摘要： Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及具有多个管芯的三维（3D）集成的集成电路（IC）封装组件，以及包含这种3D IC封装组件的相应制造方法和系统。 可以在诸如微处理器管芯的第一管芯上形成无凸起的堆积层（BBUL）封装衬底。 可以使用激光辐射在模具背面膜中形成开口，以暴露第一裸片背面的TSV焊盘。 诸如存储器管芯堆叠的第二管芯可以通过在第一和第二管芯的对应TSV之间形成的管芯互连而耦合到第一管芯。 可以施加底部填充材料以填充第一和第二管芯之间的任何剩余间隙中的一些或全部，和/或可以在第二管芯和/或封装衬底上施加密封剂。 可以描述和/或要求保护其他实施例。

公开(公告)号：US11728265B2

公开(公告)日：2023-08-15

申请号：US16129711

申请日：2018-09-12

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Frank Truong ,  Shivasubramanian Balasubramanian ,  Dilan Seneviratne ,  Yonggang Li ,  Sameer Paital ,  Darko Grujicic ,  Rengarajan Shanmugam ,  Melissa Wette ,  Srinivas Pietambaram

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L23/00 ,  H01L27/01 ,  H01L23/64

CPC分类号： H01L23/5228 ,  H01L21/4846 ,  H01L21/76871 ,  H01L23/498 ,  H01L23/5226 ,  H01L23/647 ,  H01L24/09 ,  H01L27/016 ,  H01L28/24

摘要： Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.

公开(公告)号：US20230085411A1

公开(公告)日：2023-03-16

申请号：US17477323

申请日：2021-09-16

申请人： Intel Corporation

发明人： Sameer Paital ,  Yonggang Li ,  Kristof Kuwawi Darmawikarta ,  Gang Duan ,  Srinivas V. Pietambaram

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

摘要： A microelectronic assembly is disclosed, comprising: a substrate having a core made of glass; and a first integrated circuit (IC) die and a second IC die coupled to a first side of the substrate. The core comprises a cavity, a third IC die is located within the cavity, and the core further comprises one or more conductive through-glass via (TGV) that facilitates electrical coupling between the first side of the substrate and an opposing second side of the substrate. In some embodiments, the cavity is a blind cavity; in other embodiments, the cavity is a through-hole. In some embodiments, the third IC die merely provides lateral coupling between the first IC die and the second IC die; in other embodiments, the third IC die also provides electrical coupling between the first side and the second side of the substrate with through-silicon vias.

公开(公告)号：US20200005987A1

公开(公告)日：2020-01-02

申请号：US16022894

申请日：2018-06-29

申请人： Intel Corporation

发明人： Srinivas Pietambaram ,  Kristof Darmawikarta ,  Gang Duan ,  Yonggang Li ,  Sameer Paital

IPC分类号： H01F27/26 ,  H01F27/42 ,  H01L23/64 ,  H01L21/768

摘要： Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.

公开(公告)号：US09820390B2

公开(公告)日：2017-11-14

申请号：US14566208

申请日：2014-12-10

申请人： Intel Corporation

发明人： Mihir K. Roy ,  Islam A. Salama ,  Yonggang Li

IPC分类号： H05K3/22 ,  H05K3/42 ,  H01L23/498 ,  G06F1/18 ,  H01L23/492

CPC分类号： H05K3/422 ,  G06F1/183 ,  H01L23/492 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  Y10T29/49165 ,  H01L2924/00

摘要： A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

公开(公告)号：US12027466B2

公开(公告)日：2024-07-02

申请号：US17026703

申请日：2020-09-21

申请人： Intel Corporation

发明人： Jeremy D. Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Yonggang Li ,  Leonel Arana ,  Suddhasattwa Nad ,  Haobo Chen ,  Tarek Ibrahim

IPC分类号： H01L23/538 ,  H01L21/768 ,  H05K1/11

CPC分类号： H01L23/5386 ,  H01L21/76838 ,  H01L23/5385 ,  H05K1/11

摘要： Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.