公开(公告)号：US12125777B2

公开(公告)日：2024-10-22

申请号：US16666202

申请日：2019-10-28

申请人： Intel Corporation

发明人： Zhiguo Qian ,  Gang Duan ,  Kemal Aygün ,  Jieying Kong ,  Brandon C. Marin

IPC分类号： H01L23/49 ,  H01L21/48 ,  H01L23/498 ,  H01L23/66

CPC分类号： H01L23/49838 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/66

摘要： Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first buildup layer and a second buildup layer over the first buildup layer. In an embodiment, a void is disposed through the second buildup layer. In an embodiment the electronic package further comprises a first pad over the second buildup layer. In an embodiment, the first pad covers the void.

公开(公告)号：US12027466B2

公开(公告)日：2024-07-02

申请号：US17026703

申请日：2020-09-21

申请人： Intel Corporation

发明人： Jeremy D. Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Yonggang Li ,  Leonel Arana ,  Suddhasattwa Nad ,  Haobo Chen ,  Tarek Ibrahim

IPC分类号： H01L23/538 ,  H01L21/768 ,  H05K1/11

CPC分类号： H01L23/5386 ,  H01L21/76838 ,  H01L23/5385 ,  H05K1/11

摘要： Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

公开(公告)号：US20240178162A1

公开(公告)日：2024-05-30

申请号：US18060125

申请日：2022-11-30

申请人： Intel Corporation

发明人： Jeremy Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Hiroki Tanaka

IPC分类号： H01L23/66 ,  H01L23/13 ,  H01L23/15 ,  H01L23/498

CPC分类号： H01L23/66 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2223/6616

摘要： An integrated circuit (IC) package substrate including a glass core having a cavity filter structure, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include a core made of glass, and the core including a first core portion having a first surface and a trench and a ridge in the first surface, the trench and the ridge lined with a conductive material; and a second core portion having a second surface, the second surface lined with the conductive material, wherein the first surface of the first core portion is physically coupled to the second surface of the second core portion forming a cavity filter structure.

公开(公告)号：US20240176070A1

公开(公告)日：2024-05-30

申请号：US18059057

申请日：2022-11-28

申请人： Intel Corporation

发明人： Jeremy Ecton ,  Brandon C. Marin ,  Changhua Liu ,  Srinivas V. Pietambaram ,  Hiroki Tanaka

IPC分类号： G02B6/12 ,  H01L25/16

CPC分类号： G02B6/12004 ,  H01L25/167

摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a photonic assembly may include a substrate having a core with a surface, wherein a material of the core includes glass; and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways; a photonic integrated circuit (PIC) electrically coupled to the conductive pathways in the dielectric material; a first optical component between the PIC and the surface of the core, wherein the first optical component is coupled to the surface of the core by optical glue or by fusion bonding; and a second optical component coupled to the core, wherein the second optical component is optically coupled to the PIC by an optical pathway through the core and the first optical component.

公开(公告)号：US20240079339A1

公开(公告)日：2024-03-07

申请号：US17929045

申请日：2022-09-01

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Benjamin T. Duong ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L23/5386 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L23/481 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253

摘要： Embodiments of a microelectronic assembly comprise: a package substrate including a first integrated circuit (IC) die embedded therein; and a second IC die coupled to the package substrate and conductively coupled to the first IC die by vias in the package substrate. The package substrate has a first side and an opposing second side, the second IC die is coupled to the first side of the package substrate, the first IC die is between the first side of the package substrate and the second side of the package substrate, the package substrate comprises a plurality of layers of conductive traces in an organic dielectric material, the first IC die is surrounded by the organic dielectric material of the package substrate, the vias are in the organic dielectric material between the first IC die and the first side of the package substrate, and the first IC die comprises through-substrate vias.

公开(公告)号：US20230197679A1

公开(公告)日：2023-06-22

申请号：US17558457

申请日：2021-12-21

申请人： Intel Corporation

发明人： Jeremy Ecton ,  Jason M. Gamba ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Xiaoxuan Sun ,  Omkar G. Karhade ,  Xavier Francois Brun ,  Yonggang Li ,  Suddhasattwa Nad ,  Bohan Shan ,  Haobo Chen ,  Gang Duan

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L25/0652 ,  H01L24/16 ,  H01L24/14 ,  H01L24/73 ,  H01L24/13 ,  H01L23/5383 ,  H01L2224/16227 ,  H01L2224/14177 ,  H01L2224/73204 ,  H01L2224/13111 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01031

摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

公开(公告)号：US20220406736A1

公开(公告)日：2022-12-22

申请号：US17352726

申请日：2021-06-21

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Srinivas Pietambaram ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC分类号： H01L23/64 ,  H01L23/15 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768

摘要： Disclosed herein are high-permeability magnetic thin films for coaxial metal inductor loop structures formed in through glass vias of a glass core package substrate, and related methods, devices, and systems. Exemplary coaxial metal inductor loop structures include a high-permeability magnetic layer within and on a surface of a through glass via extending through the glass core package substrate and a conductive layer on the high-permeability magnetic layer.

公开(公告)号：US11462432B2

公开(公告)日：2022-10-04

申请号：US15922749

申请日：2018-03-15

申请人： Intel Corporation

发明人： Frank Truong ,  Praneeth Akkinepally ,  Chelsea M. Groves ,  Whitney M. Bryks ,  Jason M. Gamba ,  Brandon C. Marin

IPC分类号： B32B43/00 ,  H01L21/683 ,  H01L21/687 ,  C09J5/06 ,  H01L21/02

摘要： A system is disclosed, which comprises a component carrier having a first side, and a second side opposite the first side; and a light source to couple light into the carrier. In an example, the carrier is to propagate, through internal reflection, at least a portion the light to both the first and second sides of the carrier. The portion of light may be sufficient to release a first component and second component affixed to the first and second sides of the carrier via a first photosensitive layer and second photosensitive layer, respectively.

公开(公告)号：US20200312793A1

公开(公告)日：2020-10-01

申请号：US16369708

申请日：2019-03-29

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D. Ecton

IPC分类号： H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L49/02

摘要： A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

公开(公告)号：US20200006468A1

公开(公告)日：2020-01-02

申请号：US16024223

申请日：2018-06-29

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Praneeth Akkinepally ,  Whitney Bryks ,  Dilan Seneviratne ,  Frank Truong

IPC分类号： H01L49/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00

摘要： Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.