公开(公告)号：US20250105156A1

公开(公告)日：2025-03-27

申请号：US18473479

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Bohan Shan ,  Gang Duan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L25/065

Abstract: Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface, the glass layer including conductive through-glass vias (TGVs); a dielectric layer at the surface of the glass layer, the dielectric layer including conductive pathways; and interconnects between the surface of the glass layer and the dielectric layer, wherein individual interconnects electrically couple individual TGVs to individual conductive pathways. In some embodiments, the interconnects include solder or liquid metal ink. In some embodiments, the interconnects include metal-metal bonds and dielectric-dielectric bonds.

公开(公告)号：US20250096053A1

公开(公告)日：2025-03-20

申请号：US18470645

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Bohan Shan ,  Tarek A. Ibrahim ,  Srinivas V. Pietambaram ,  Gang Duan ,  Benjamin T. Duong ,  Suddhasattwa Nad

IPC: H01L23/15 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065

Abstract: A microelectronic assembly includes an embedded bridge die and a glass structure, such as glass patch, under the bridge die. The bridge die and the glass structure are embedded in a substrate. The assembly may further include two or more dies arranged over the substrate and coupled to the bridge die. The glass structure may include through-glass vias, and vias in the substrate below the glass structure are self-aligned to the through-glass vias. The glass structure may include an embedded passive device, such as an embedded inductor or capacitor.

公开(公告)号：US20250079266A1

公开(公告)日：2025-03-06

申请号：US18456615

申请日：2023-08-28

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Jeremy Ecton

IPC: H01L23/482 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate having a blind cavity between a first surface and a second opposing surface; a bridge die in the blind cavity, the blind cavity being open towards the first surface; and a plurality of integrated circuit (IC) dies coupled to the first surface and to the bridge die. The blind cavity has a floor and a plurality of sidewalls, at least one sidewall is at an obtuse angle to the floor, and the at least one sidewall is patterned with conductive traces.

公开(公告)号：US12224253B2

公开(公告)日：2025-02-11

申请号：US17480064

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Xin Ning ,  Brandon C. Marin ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Numair Ahmed ,  Brent Williams ,  Mollie Stewart ,  Nathan Ou ,  Cary Kuliasha

IPC: H01L23/64 ,  H01F27/28 ,  H01L21/48 ,  H01L23/498 ,  H01L49/02

Abstract: Transmission pathways in substrates, and associated methods are shown. Example transmission pathways include a semiconductor substrate with a core, a dielectric layer fixed on the core, at least one first electrical transmission pathway extending through at least one of the dielectric layer and the core. The first pathway includes a magnetic material disposed within the at least the core of the at least one first electrical transmission pathway, at least one second electrical transmission pathway extending through the magnetic material, a nickel layer disposed on inner circumferential surface of the magnetic material at least within the second electrical transmission pathway, a copper layer disposed on at least the nickel layer within the second electrical transmission pathway. The dielectric spacer or the nickel layer separates the copper layer from the magnetic material. At least one third pathway extends through at least one of the dielectric layer and the core separate from the at least one electrical transmission pathway.

公开(公告)号：US20240395661A1

公开(公告)日：2024-11-28

申请号：US18202046

申请日：2023-05-25

Applicant: Intel Corporation

Inventor： Numair Ahmed ,  Suddhasattwa Nad ,  Mohammad Mamunur Rahman ,  Brandon C. Marin ,  Sashi S. Kandanur ,  Srinivas Venkata Ramanuja Pietambaram ,  Darko Grujicic ,  Gang Duan ,  Banjamin Duong

IPC: H01L23/473 ,  H01L23/31 ,  H01L23/373 ,  H01L23/48 ,  H01L23/498

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a glass core layer having a first surface layer and a second surface layer; multiple channels within the glass core layer between the first surface and the second surface layer; and a first redistribution layer (RDL) including multiple sublayers of conductive traces formed in an organic material, wherein a first surface of the RDL contacts the first surface of the glass core layer.

公开(公告)号：US12125777B2

公开(公告)日：2024-10-22

申请号：US16666202

申请日：2019-10-28

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Gang Duan ,  Kemal Aygün ,  Jieying Kong ,  Brandon C. Marin

IPC: H01L23/49 ,  H01L21/48 ,  H01L23/498 ,  H01L23/66

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/66

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first buildup layer and a second buildup layer over the first buildup layer. In an embodiment, a void is disposed through the second buildup layer. In an embodiment the electronic package further comprises a first pad over the second buildup layer. In an embodiment, the first pad covers the void.

公开(公告)号：US12027466B2

公开(公告)日：2024-07-02

申请号：US17026703

申请日：2020-09-21

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Yonggang Li ,  Leonel Arana ,  Suddhasattwa Nad ,  Haobo Chen ,  Tarek Ibrahim

IPC: H01L23/538 ,  H01L21/768 ,  H05K1/11

CPC classification number: H01L23/5386 ,  H01L21/76838 ,  H01L23/5385 ,  H05K1/11

Abstract: Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

公开(公告)号：US20240178162A1

公开(公告)日：2024-05-30

申请号：US18060125

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Hiroki Tanaka

IPC: H01L23/66 ,  H01L23/13 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2223/6616

Abstract: An integrated circuit (IC) package substrate including a glass core having a cavity filter structure, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include a core made of glass, and the core including a first core portion having a first surface and a trench and a ridge in the first surface, the trench and the ridge lined with a conductive material; and a second core portion having a second surface, the second surface lined with the conductive material, wherein the first surface of the first core portion is physically coupled to the second surface of the second core portion forming a cavity filter structure.

公开(公告)号：US20240176070A1

公开(公告)日：2024-05-30

申请号：US18059057

申请日：2022-11-28

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Changhua Liu ,  Srinivas V. Pietambaram ,  Hiroki Tanaka

IPC: G02B6/12 ,  H01L25/16

CPC classification number: G02B6/12004 ,  H01L25/167

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a photonic assembly may include a substrate having a core with a surface, wherein a material of the core includes glass; and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways; a photonic integrated circuit (PIC) electrically coupled to the conductive pathways in the dielectric material; a first optical component between the PIC and the surface of the core, wherein the first optical component is coupled to the surface of the core by optical glue or by fusion bonding; and a second optical component coupled to the core, wherein the second optical component is optically coupled to the PIC by an optical pathway through the core and the first optical component.

公开(公告)号：US20240079339A1

公开(公告)日：2024-03-07

申请号：US17929045

申请日：2022-09-01

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Benjamin T. Duong ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L23/481 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate including a first integrated circuit (IC) die embedded therein; and a second IC die coupled to the package substrate and conductively coupled to the first IC die by vias in the package substrate. The package substrate has a first side and an opposing second side, the second IC die is coupled to the first side of the package substrate, the first IC die is between the first side of the package substrate and the second side of the package substrate, the package substrate comprises a plurality of layers of conductive traces in an organic dielectric material, the first IC die is surrounded by the organic dielectric material of the package substrate, the vias are in the organic dielectric material between the first IC die and the first side of the package substrate, and the first IC die comprises through-substrate vias.