Invention Grant
- Patent Title: Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate
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Application No.: US18171540Application Date: 2023-02-20
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Publication No.: US12237014B2Publication Date: 2025-02-25
- Inventor: Takatoshi Minamoto , Toshiki Hisada , Dai Nakamura
- Applicant: KIOXIA CORPORATION
- Applicant Address: JP Tokyo
- Assignee: KIOXIA CORPORATION
- Current Assignee: KIOXIA CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2009-019678 20090130
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/08 ; G11C16/10 ; G11C16/24 ; H01L23/528 ; H10B41/10 ; H10B41/35 ; H10B43/10 ; H10B43/35

Abstract:
A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M
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