公开(公告)号：US12193225B2

公开(公告)日：2025-01-07

申请号：US17369453

申请日：2021-07-07

Applicant: Kioxia Corporation

Inventor： Takatoshi Minamoto ,  Sho Tokairin ,  Yoshinao Suzuki

IPC: H01L27/11556 ,  G11C5/02 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor device has a first conductivity type semiconductor substrate. A second conductivity type first impurity diffusion layer is disposed in a surface region of the semiconductor substrate. A resistance element is configured with a first conductivity type second impurity diffusion layer disposed in the first impurity diffusion layer in the surface region of the semiconductor substrate. In a transistor, a gate is connected to an input portion of the resistance element, a source is connected to the first impurity diffusion layer, and a drain is connected to a voltage source higher than the voltage of the input portion. A current source is connected to the source.

公开(公告)号：US11610630B2

公开(公告)日：2023-03-21

申请号：US17204572

申请日：2021-03-17

Applicant: Kioxia Corporation

Inventor： Takatoshi Minamoto ,  Toshiki Hisada ,  Dai Nakamura

IPC: G11C16/04 ,  H01L27/11519 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M

公开(公告)号：US12237014B2

公开(公告)日：2025-02-25

申请号：US18171540

申请日：2023-02-20

Applicant: KIOXIA CORPORATION

Inventor： Takatoshi Minamoto ,  Toshiki Hisada ,  Dai Nakamura

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M