公开(公告)号：US11610630B2

公开(公告)日：2023-03-21

申请号：US17204572

申请日：2021-03-17

Applicant: Kioxia Corporation

Inventor： Takatoshi Minamoto ,  Toshiki Hisada ,  Dai Nakamura

IPC: G11C16/04 ,  H01L27/11519 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M

公开(公告)号：US12197732B2

公开(公告)日：2025-01-14

申请号：US17898370

申请日：2022-08-29

Applicant: KIOXIA CORPORATION

Inventor： Kenta Shibasaki ,  Yoshihiko Shindo ,  Yasuhiro Hirashima ,  Akio Sugahara ,  Shigeki Nagasaka ,  Dai Nakamura ,  Yousuke Hagiwara

IPC: G06F3/06

Abstract: A memory system includes a memory chip and a memory controller. The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller.

公开(公告)号：USRE49274E1

公开(公告)日：2022-11-01

申请号：US16284203

申请日：2019-02-25

Applicant: KIOXIA CORPORATION

Inventor： Dai Nakamura ,  Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Takeshi Shimane ,  Mitsuhiro Noguchi ,  Koji Hosono ,  Masaru Koyanagi ,  Takashi Aoi

IPC: G11C16/04 ,  G11C16/24

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

公开(公告)号：US12237014B2

公开(公告)日：2025-02-25

申请号：US18171540

申请日：2023-02-20

Applicant: KIOXIA CORPORATION

Inventor： Takatoshi Minamoto ,  Toshiki Hisada ,  Dai Nakamura

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M

公开(公告)号：US11209846B2

公开(公告)日：2021-12-28

申请号：US16941801

申请日：2020-07-29

Applicant: Kioxia Corporation

Inventor： Kazuhiko Satou ,  Tomonori Kurosawa ,  Dai Nakamura

IPC: G05F1/46 ,  G05F1/648

Abstract: In one embodiment, a semiconductor device includes a reference voltage supply circuit configured to supply a first reference voltage and a second reference voltage. The device further includes a power source voltage supply circuit including a first power source voltage generator supplied with the first reference voltage and configured to generate a first power source voltage, and a second power source voltage generator supplied with the second reference voltage and configured to generate a second power source voltage, the power source voltage supply circuit being configured to supply the first power source voltage and the second power source voltage to a power source voltage line. The device further includes a voltage control circuit connected to the power source voltage line, and configured to control a value of the first reference voltage and a value the second reference voltage.

公开(公告)号：US11139039B2

公开(公告)日：2021-10-05

申请号：US16816900

申请日：2020-03-12

Applicant: Kioxia Corporation

Inventor： Tomonori Kurosawa ,  Dai Nakamura

IPC: G11C16/34 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04

Abstract: According to one embodiment, a memory device includes a memory cell, a word line connected to the memory cell, a word line driver which generates a selection signal for the word line, a first transistor including a gate to which the selection signal generated by the word line driver is input, and a drain which supplies a signal based on the selection signal to the word line, and a detection circuit which detects a value based on a current flowing through the first transistor during a verification period after writing data to the memory cell.