A digital-to-time converter (DTC)-based open loop frequency synthesis and calibration circuit may be used to provide a precise clock signal. The DTC calibration circuit may include a DTC to generate a DTC clock signal based on a received input clock frequency and a received initial digital input code, a phase-lock loop (PLL) to generate a PLL clock signal based on a received PLL input, a binary phase-detector (PD) to generate a PD output based on a comparison between the DTC clock signal and the PLL clock signal, a plurality of calibration bins to generate a signed accumulated PD portion based on the PD output, and an adder to generate a calibrated DTC input code based on a combination of the signed accumulated PD portion and a subsequent digital input code, where the DTC generates a calibrated clock signal based on the calibrated DTC input code.