公开(公告)号：US20230098856A1

公开(公告)日：2023-03-30

申请号：US17481827

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Somnath Kundu ,  Stefano Pellerano ,  Brent R. Carlton

IPC: H03L7/197 ,  H03L7/099 ,  H03L7/091

Abstract: A digital-to-time converter (DTC)-based open loop frequency synthesis and calibration circuit may be used to provide a precise clock signal. The DTC calibration circuit may include a DTC to generate a DTC clock signal based on a received input clock frequency and a received initial digital input code, a phase-lock loop (PLL) to generate a PLL clock signal based on a received PLL input, a binary phase-detector (PD) to generate a PD output based on a comparison between the DTC clock signal and the PLL clock signal, a plurality of calibration bins to generate a signed accumulated PD portion based on the PD output, and an adder to generate a calibrated DTC input code based on a combination of the signed accumulated PD portion and a subsequent digital input code, where the DTC generates a calibrated clock signal based on the calibrated DTC input code.

公开(公告)号：US20230198510A1

公开(公告)日：2023-06-22

申请号：US17558056

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Amy Whitcombe ,  Somnath Kundu ,  Brent R. Carlton

IPC: H03K4/94 ,  H03K5/01 ,  H03F3/45 ,  H03K19/20

CPC classification number: H03K4/94 ,  H03K5/01 ,  H03F3/45475 ,  H03K19/20

Abstract: A differential voltage-to-time converter (VTC) architecture and method of providing VTC signals are disclosed. The VTC includes a ramp generator that generates a ramp voltage, capacitors having a bottom plate coupled with the ramp generator to receive the ramp voltage, and inverters having inputs coupled to top plates of the capacitors to provide signals based on a sampled signal. A threshold voltage or supply voltage of the inverters tracks a minimum input signal voltage.

公开(公告)号：US11277143B1

公开(公告)日：2022-03-15

申请号：US17024419

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Somnath Kundu ,  Abhishek Agrawal ,  Brent Carlton

IPC: H03L7/197 ,  H03L7/099 ,  H03L7/091

Abstract: A reference sampling Type-I fractional-N PLL directly samples the reference clock and therefore does not use a reference buffer. Here, a phase-detector is a passive sampling switch which neither consumes any power nor generates any noise. Therefore, all the major contributors of in-band phase-noise are eliminated by the reference sampling Type-I fractional-N divider. A double sampling phase-detector with a switched-capacitor passive voltage interpolator circuit is used to achieve fractional-N output. To achieve a high resolution of the voltage interpolator or the switched capacitor, a sigma-delta modulator is used.

公开(公告)号：US20240235561A9

公开(公告)日：2024-07-11

申请号：US17970477

申请日：2022-10-20

Applicant: Intel Corporation

Inventor： Hao Luo ,  Somnath Kundu ,  Brent R. Carlton

IPC: H03L7/099 ,  H03L7/093

CPC classification number: H03L7/0992 ,  H03L7/093 ,  H03L2207/50

Abstract: Embodiments herein relate to a sampling phase-locked loop (PLL) with a compensation circuit for reducing ripples due to the use of a fractional N divider. The compensation circuit includes a ripple amplifier and a ripple divider. The ripple amplifier receives an output voltage, Vmain, of a main sampling circuit of the PLL and amplifies its alternating current (AC) components. The amplified output voltage is provided to a ripple integrator which samples the minimum and maximum values to provide inputs to an operational amplifier (op amp). An output of the op amp is fed back to a digital-to-analog converter (DAC), which provides a corresponding compensation voltage, Vcomp. Vcomp is added to Vmain to provide a final output control voltage, Vctrl, to control a voltage-controlled oscillator (VCO) of the PLL.

公开(公告)号：US20220229495A1

公开(公告)日：2022-07-21

申请号：US17711905

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Hao Luo ,  Somnath Kundu ,  Brent Carlton ,  Zhen Zhou

IPC: G06F3/01 ,  G06F3/0488 ,  G01S13/89

Abstract: Techniques for radiofrequency (RF) touch and gesture recognition are disclosed. In the illustrative embodiment, RF transmitters and receivers are connected to data lines and gate lines of a display. RF signals sent on one data or gate line may be scattered to a different data or gate line based on the presence of a nearby object, such as a finger. The amount of scattering on different data or gate lines can be used to determine a location of one or more objects.

公开(公告)号：US20200083892A1

公开(公告)日：2020-03-12

申请号：US16126722

申请日：2018-09-10

Applicant: Intel Corporation

Inventor： Somnath Kundu ,  Stefano Pellerano ,  Abhishek Agrawal

IPC: H03L7/087 ,  H03L7/099 ,  H03L7/113

Abstract: A sub-sampler phase locked loop (SSPLL) system having a frequency locking loop (FLL) and a phase locked loop (PLL) is disclosed. The FLL is configured to detect frequency variations between a phase locked loop (PLL) output signal and a reference frequency and automatically generate a pulsed correction signal upon the detected frequency variations and apply the pulsed correction signal to a voltage controlled oscillator (VCO) control voltage. The PLL is configured to generate the PLL output signal based on the VCO control voltage.

公开(公告)号：US20220393688A1

公开(公告)日：2022-12-08

申请号：US17338497

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Somnath Kundu ,  Hao Luo ,  Brent Carlton

IPC: H03L7/099

Abstract: An apparatus and method are provided to re-configure an existing low-jitter phase locked loop (PLL) circuit for fast start-up during system wake-up. During system start-up, a feed-back path of the PLL is disconnected to independently control the VCO frequency. This independently controlled VCO then injects energy into a resonator (e.g., a crustal oscillator) for its fast start-up. Once a resonance frequency of the resonator is detected and an oscillation builds up in the resonator, a VCO control voltage is stored. The PLL feedback is then restored and the stored VCO control voltage is applied to perform phase-locking operation. Since the PLL control voltage is already set to the desired operating point, the PLL lock time is very small.

公开(公告)号：US20220085822A1

公开(公告)日：2022-03-17

申请号：US17024419

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Somnath Kundu ,  Abhishek Agrawal ,  Brent Carlton

IPC: H03L7/197 ,  H03L7/091 ,  H03L7/099

Abstract: A reference sampling Type-I fractional-N PLL directly samples the reference clock and therefore does not use a reference buffer. Here, a phase-detector is a passive sampling switch which neither consumes any power nor generates any noise. Therefore, all the major contributors of in-band phase-noise are eliminated by the reference sampling Type-I fractional-N divider. A double sampling phase-detector with a switched-capacitor passive voltage interpolator circuit is used to achieve fractional-N output. To achieve a high resolution of the voltage interpolator or the switched capacitor, a sigma-delta modulator is used.

公开(公告)号：US20200295765A1

公开(公告)日：2020-09-17

申请号：US16352043

申请日：2019-03-13

Applicant: Intel Corporation

Inventor： Abhishek Agrawal ,  Alon Cohen ,  Gil Horovitz ,  Somnath Kundu ,  Run Levinger ,  Stefano Pellerano ,  Jahnavi Sharma ,  Evgeny Shumaker ,  Izhak Hod

IPC: H03L7/081 ,  H03L7/083

Abstract: A quadrature based voltage controlled oscillator (VCO) local oscillator (LO) system is disclosed. The system includes a phase detector, a quadrature phase VCO, a quadrature control path, an in-phase control path, and an in-phase VCO. The phase detector is configured to compare and generate phase error between a reference clock and an in-phase VCO output. The quadrature control path configured to generate a quadrature control voltage based on a quadrature VCO output and the in-phase VCO output. The quadrature phase VCO configured to generate the quadrature VCO output based on the quadrature control voltage and the generated phase error. The in-phase control path configured to generate an in-phase control voltage based on the quadrature VCO output and the in-phase VCO output. The in-phase VCO is configured to generate the in-phase VCO output based on the in-phase control voltage and the generated phase error. An all digital dual mode phase locked/phase tracking loop LO generate system is also disclosed.

公开(公告)号：US12249997B2

公开(公告)日：2025-03-11

申请号：US17338497

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Somnath Kundu ,  Hao Luo ,  Brent Carlton

IPC: H03L7/099

Abstract: An apparatus and method are provided to re-configure an existing low-jitter phase locked loop (PLL) circuit for fast start-up during system wake-up. During system start-up, a feed-back path of the PLL is disconnected to independently control the VCO frequency. This independently controlled VCO then injects energy into a resonator (e.g., a crustal oscillator) for its fast start-up. Once a resonance frequency of the resonator is detected and an oscillation builds up in the resonator, a VCO control voltage is stored. The PLL feedback is then restored and the stored VCO control voltage is applied to perform phase-locking operation. Since the PLL control voltage is already set to the desired operating point, the PLL lock time is very small.