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公开(公告)号：US20250007501A1
公开(公告)日：2025-01-02
申请号：US18214885
申请日：2023-06-27
Applicant: Intel Corporation
Inventor： Eduardo Alban , Hao Luo , Nasser A. Kurd , Kedar Mangrulkar , Mohamed A. Abdelmoneum , Brent R. Carlton
IPC: H03K5/1252 , G06F1/06 , H03B5/36
Abstract: An apparatus includes an oscillator circuit and a low-pass filter circuit coupled to an output terminal of the oscillator circuit. The apparatus further includes a first digital signal generator coupled to at least one of an output terminal of the low-pass filter circuit and the output terminal of the oscillator circuit and a second digital signal generator coupled to at least one of the output terminal of the low-pass filter circuit and the output terminal of the oscillator circuit. The second digital signal generator generates a second digital clock signal based on a non-differential signal output of the oscillator circuit. The apparatus further includes a radio frequency interference (RFI) detection circuit coupled to the first digital signal generator and the second digital signal generator. The RFI detection circuit detects RFI associated with the non-differential signal output of the oscillator circuit.
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公开(公告)号：US20240235561A9
公开(公告)日：2024-07-11
申请号：US17970477
申请日：2022-10-20
Applicant: Intel Corporation
Inventor： Hao Luo , Somnath Kundu , Brent R. Carlton
CPC classification number: H03L7/0992 , H03L7/093 , H03L2207/50
Abstract: Embodiments herein relate to a sampling phase-locked loop (PLL) with a compensation circuit for reducing ripples due to the use of a fractional N divider. The compensation circuit includes a ripple amplifier and a ripple divider. The ripple amplifier receives an output voltage, Vmain, of a main sampling circuit of the PLL and amplifies its alternating current (AC) components. The amplified output voltage is provided to a ripple integrator which samples the minimum and maximum values to provide inputs to an operational amplifier (op amp). An output of the op amp is fed back to a digital-to-analog converter (DAC), which provides a corresponding compensation voltage, Vcomp. Vcomp is added to Vmain to provide a final output control voltage, Vctrl, to control a voltage-controlled oscillator (VCO) of the PLL.
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公开(公告)号：US20240137029A1
公开(公告)日：2024-04-25
申请号：US17970477
申请日：2022-10-19
Applicant: Intel Corporation
Inventor： Hao Luo , Somnath Kundu , Brent R. Carlton
CPC classification number: H03L7/0992 , H03L7/093 , H03L2207/50
Abstract: Embodiments herein relate to a sampling phase-locked loop (PLL) with a compensation circuit for reducing ripples due to the use of a fractional N divider. The compensation circuit includes a ripple amplifier and a ripple divider. The ripple amplifier receives an output voltage, Vmain, of a main sampling circuit of the PLL and amplifies its alternating current (AC) components. The amplified output voltage is provided to a ripple integrator which samples the minimum and maximum values to provide inputs to an operational amplifier (op amp). An output of the op amp is fed back to a digital-to-analog converter (DAC), which provides a corresponding compensation voltage, Vcomp. Vcomp is added to Vmain to provide a final output control voltage, Vctrl, to control a voltage-controlled oscillator (VCO) of the PLL.
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公开(公告)号：US20240007050A1
公开(公告)日：2024-01-04
申请号：US17854534
申请日：2022-06-30
Applicant: Intel Corporation
Inventor： Timo Huusari , Mohamed A. Abdelmoneum , Brent R. Carlton , Somnath Kundu , Hao Luo , Sarah Shahraini , Jason Mix , Eduardo Alban
CPC classification number: H03B5/36 , H03B5/06 , H03B2200/0094
Abstract: An apparatus, system, and method for multi-frequency oscillator control are provided. A circuit can include a resonator circuit including an input and an output, the resonator circuit configured to resonate at a fundamental frequency and a different, non-fundamental frequency, a startup circuit electrically coupled to the input, the startup circuit configured to generate a signal at about the non-fundamental frequency and detect when the resonator circuit is resonating at the non-fundamental frequency, and an oscillator driver circuit electrically coupled to the output, the oscillator driver circuit configured to amplify and buffer the output of resonator circuit and drive a load.
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Patent Agency Ranking
公开(公告)号：US12278643B2
公开(公告)日：2025-04-15
申请号：US17481827
申请日：2021-09-22
Applicant: Intel Corporation
Inventor： Somnath Kundu , Stefano Pellerano , Brent R. Carlton
Abstract: A digital-to-time converter (DTC)-based open loop frequency synthesis and calibration circuit may be used to provide a precise clock signal. The DTC calibration circuit may include a DTC to generate a DTC clock signal based on a received input clock frequency and a received initial digital input code, a phase-lock loop (PLL) to generate a PLL clock signal based on a received PLL input, a binary phase-detector (PD) to generate a PD output based on a comparison between the DTC clock signal and the PLL clock signal, a plurality of calibration bins to generate a signed accumulated PD portion based on the PD output, and an adder to generate a calibrated DTC input code based on a combination of the signed accumulated PD portion and a subsequent digital input code, where the DTC generates a calibrated clock signal based on the calibrated DTC input code.
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公开(公告)号：US12095712B2
公开(公告)日：2024-09-17
申请号：US17131862
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Brent R. Carlton , Asma Beevi Kuriparambil Thekkumpate , Renzhi Liu , Rinkle Jain
CPC classification number: H04L5/1461 , H04B1/44 , H04L5/143 , H04L25/03834 , H04W52/0235 , H04W74/008
Abstract: A transceiver may include a transmitter device, a receiver device, a secondary receiver device, and switching elements. The transmitter device may provide a transmit control signal on first and second channels. The receiver device may receive a receive control signal on the first and second channels. The secondary receiver device may monitor occupation of the first and second channels without decoding at least a portion of control signals concurrent with the receiver device receiving the receive control signal. The switching elements may control when the transmitter device provides the transmit control signal to one of and is electrically isolated from first and second antennas, the receiver device receives the receive control signal from one of and is electrically isolated from the first and second antennas, and the secondary receiver device monitors occupation of one of the first and second channels and is electrically isolated from the first and second antennas.
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公开(公告)号：US20230198510A1
公开(公告)日：2023-06-22
申请号：US17558056
申请日：2021-12-21
Applicant: Intel Corporation
Inventor： Amy Whitcombe , Somnath Kundu , Brent R. Carlton
CPC classification number: H03K4/94 , H03K5/01 , H03F3/45475 , H03K19/20
Abstract: A differential voltage-to-time converter (VTC) architecture and method of providing VTC signals are disclosed. The VTC includes a ramp generator that generates a ramp voltage, capacitors having a bottom plate coupled with the ramp generator to receive the ramp voltage, and inverters having inputs coupled to top plates of the capacitors to provide signals based on a sampled signal. A threshold voltage or supply voltage of the inverters tracks a minimum input signal voltage.
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公开(公告)号：US12212351B2
公开(公告)日：2025-01-28
申请号：US17131872
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Abhishek Agrawal , Ritesh A. Bhat , Steven Callender , Brent R. Carlton , Christopher D. Hull , Stefano Pellerano , Mustafijur Rahman , Peter Sagazio , Woorim Shin
IPC: H04B1/04
Abstract: Various aspects provide a transceiver and a communication device including the transceiver. In an example, the transceiver includes an amplifier circuit including an amplifier stage with an adjustable degeneration component, the amplifier stage configured to amplify a received input signal with an adjustable gain, an adjustable feedback component coupled to the amplifier stage; and a controller coupled to the amplifier stage and to the adjustable feedback component and configured to adjust the adjustable feedback component based on an adjustment of the adjustable degeneration component.
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公开(公告)号：US20230098856A1
公开(公告)日：2023-03-30
申请号：US17481827
申请日：2021-09-22
Applicant: Intel Corporation
Inventor： Somnath Kundu , Stefano Pellerano , Brent R. Carlton
Abstract: A digital-to-time converter (DTC)-based open loop frequency synthesis and calibration circuit may be used to provide a precise clock signal. The DTC calibration circuit may include a DTC to generate a DTC clock signal based on a received input clock frequency and a received initial digital input code, a phase-lock loop (PLL) to generate a PLL clock signal based on a received PLL input, a binary phase-detector (PD) to generate a PD output based on a comparison between the DTC clock signal and the PLL clock signal, a plurality of calibration bins to generate a signed accumulated PD portion based on the PD output, and an adder to generate a calibrated DTC input code based on a combination of the signed accumulated PD portion and a subsequent digital input code, where the DTC generates a calibrated clock signal based on the calibrated DTC input code.
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