Invention Application
US20030008486A1 Method of fabricating a MOS transistor with a drain extension and corresponding transistor
有权
制造具有漏极延伸的MOS晶体管和对应的晶体管的方法
- Patent Title: Method of fabricating a MOS transistor with a drain extension and corresponding transistor
- Patent Title (中): 制造具有漏极延伸的MOS晶体管和对应的晶体管的方法
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Application No.: US10184036Application Date: 2002-06-27
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Publication No.: US20030008486A1Publication Date: 2003-01-09
- Inventor: Thierry Schwartzmann , Herve Jaouen
- Applicant: STMicroelectronics S.A.
- Applicant Address: FR Montrouge
- Assignee: STMicroelectronics S.A.
- Current Assignee: STMicroelectronics S.A.
- Current Assignee Address: FR Montrouge
- Priority: FR0108677 20010629
- Main IPC: H01L021/28
- IPC: H01L021/28
Abstract:
A MOS transistor with a drain extension includes an isolation block on the upper surface of a semiconductor substrate. The isolation block has a first sidewall next to the gate of the transistor, and a second sidewall that is substantially parallel to the first sidewall. The isolation block further includes a drain extension zone in the substrate under the isolation block, and a drain region in contact with the drain extension zone. The drain region is in the substrate but is not covered by the isolation block.
Public/Granted literature
- US06800514B2 Method of fabricating a MOS transistor with a drain extension and corresponding transistor Public/Granted day:2004-10-05
Information query
