公开(公告)号：US20020019083A1

公开(公告)日：2002-02-14

申请号：US09915753

申请日：2001-07-26

Applicant: STMicroelectronics S.A.

Inventor： Herve Jaouen ,  Vincent Le Goascoz

IPC: H01L021/84 ,  H01L021/00 ,  H01L021/331 ,  H01L021/8222

CPC classification number: H01L21/76264 ,  H01L21/76275 ,  H01L21/76278

Abstract: A method of fabricating, from a first semiconductor substrate having two parallel main surfaces, a system including an islet of a semiconductor material surrounded by an insulative material and resting on another insulative material includes forming a layer of a first insulative material, and forming on the top main surface of the first semiconductor substrate a thin semiconductor layer forming the islet of semiconductor material. The thin semiconductor layer can be selectively etched relative to the first semiconductor substrate. A layer of a second insulative material is formed on exposed surfaces of the islet of semiconductor material and the thin semiconductor layer. The method further includes removing the first semiconductor substrate.

Abstract translation: 从具有两个平行主表面的第一半导体衬底制造包括由绝缘材料包围并放置在另一绝缘材料上的半导体材料的胰岛的系统的方法包括形成第一绝缘材料层，并在 第一半导体衬底的顶部主表面是形成半导体材料的小岛的薄的半导体层。 可以相对于第一半导体衬底选择性地蚀刻薄半导体层。 在半导体材料的胰岛和薄半导体层的暴露表面上形成第二绝缘材料层。 该方法还包括移除第一半导体衬底。

公开(公告)号：US20040217305A1

公开(公告)日：2004-11-04

申请号：US10778323

申请日：2004-02-13

Applicant: STMicroelectronics S.A.

Inventor： Jean-Pierre Schoellkopf ,  Herve Jaouen

IPC: G21G005/00

CPC classification number: H01L21/76807 ,  H01L21/76801 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of repairing a defect in an integrated electronic circuit caused by an incorrect lithographic mask includes the formation of an electrical isolation between two conducting parts of the circuit. The electrical isolation is obtained by at least partly filling, with an electrically insulating material, a volume hollowed out beforehand which would otherwise, and incorrectly, form an electrical connection between the two conducting parts. To do this, a mask having an aperture revealing the hollowed out volume is formed on the circuit, and the mask used to direct the filling of the electrically insulating material and correction of the lithography defined defect.

Abstract translation: 修复由不正确的光刻掩模引起的集成电子电路中的缺陷的方法包括在电路的两个导电部分之间形成电隔离。 电隔离是通过用电绝缘材料至少部分地填充预先挖空的体积获得的，否则并且不正确地在两个导电部件之间形成电连接。 为此，在电路上形成具有露出掏空体积的孔径的掩模，以及用于引导电绝缘材料的填充的掩模和校正光刻限定的缺陷。

公开(公告)号：US20030008486A1

公开(公告)日：2003-01-09

申请号：US10184036

申请日：2002-06-27

Applicant: STMicroelectronics S.A.

Inventor： Thierry Schwartzmann ,  Herve Jaouen

IPC: H01L021/28

CPC classification number: H01L29/66659 ,  H01L29/7835

Abstract: A MOS transistor with a drain extension includes an isolation block on the upper surface of a semiconductor substrate. The isolation block has a first sidewall next to the gate of the transistor, and a second sidewall that is substantially parallel to the first sidewall. The isolation block further includes a drain extension zone in the substrate under the isolation block, and a drain region in contact with the drain extension zone. The drain region is in the substrate but is not covered by the isolation block.

Abstract translation: 具有漏极延伸的MOS晶体管包括在半导体衬底的上表面上的隔离块。 隔离块具有靠近晶体管的栅极的第一侧壁和基本上平行于第一侧壁的第二侧壁。 隔离块还包括在隔离块下方的衬底中的漏极延伸区域和与漏极延伸区域接触的漏极区域。 漏极区在衬底中，但不被隔离块覆盖。

公开(公告)号：US20030025125A1

公开(公告)日：2003-02-06

申请号：US10142249

申请日：2002-05-09

Applicant: STMICROELECTRONICS S.A.

Inventor： Olivier Menut ,  Herve Jaouen

IPC: H01L029/74

CPC classification number: H01L29/1012 ,  H01L29/0649 ,  H01L29/735

Abstract: The transistor includes an emitter region 17 disposed in a first isolating well 11, 150 formed in a semiconductor bulk. An extrinsic collector region 16 is disposed in a second isolating well 3, 150 formed in the semiconductor bulk SB and separated laterally from the first well by a bulk separator area 20. An intrinsic collector region is situated in the bulk separator area 20 in contact with the extrinsic collector region. An intrinsic base region 100 is formed which is thinner laterally than vertically and in contact with the intrinsic collector region and in contact with the emitter region through bearing on a vertical flank of the first isolating well facing a vertical flank of the second isolating well. An extrinsic base region 60 is formed which is substantially perpendicular to the intrinsic base region in the top part of the bulk separator area, and contact terminals C, B, E respectively in contact with the extrinsic collector region, the extrinsic base region, and the emitter region.

Abstract translation: 晶体管包括设置在半导体本体中形成的第一隔离阱11,150中的发射极区17。 非本征集电极区域16设置在形成于半导体本体SB中的第二隔离阱3,150中，并通过体分离器区域20与第一阱的横向分离。本体集电极区域位于与本体分离器区域20接触的本体分离器区域20中 外部集电极区域。 形成本征基区100，其横向比垂直地更薄并且与本征收集区相接触，并且通过轴承在第一隔离井的垂直侧面与第二隔离井的垂直侧面的垂直侧面接触。 形成基本上垂直于本体分离器区域的顶部中的本征基极区域的外部基极区域60，以及分别与外部基极区域，外部基极区域和外部基极区域接触的接触端子C，B，E 发射区。

公开(公告)号：US20030013262A1

公开(公告)日：2003-01-16

申请号：US10171102

申请日：2002-06-13

Applicant: STMICROELECTRONICS S.A.

Inventor： Olivier Menut ,  Herve Jaouen

IPC: H01L021/331 ,  H01L021/22 ,  H01L021/38

CPC classification number: H01L29/66272

Abstract: A method of fabricating an integrated circuit including a monocrystalline silicon substrate, a layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion, in which method annealing is performed at a temperature and for a time such that a first dopant diffuses into a first zone and a second dopant diffuses into a second zone larger than the first zone.

Abstract translation: 一种制造集成电路的方法，该集成电路包括单晶硅衬底，在该衬底的顶表面上的多晶硅层，并且掺杂有至少两种具有不同扩散速率的掺杂剂，其中在温度和 时间，使得第一掺杂剂扩散到第一区域中，并且第二掺杂剂扩散到大于第一区域的第二区域中。

公开(公告)号：US20020109188A1

公开(公告)日：2002-08-15

申请号：US10044829

申请日：2002-01-11

Applicant: STMICROELECTRONICS S.A.

Inventor： Olivier Menut ,  Guillaume Bouche ,  Herve Jaouen

IPC: H01L027/01

CPC classification number: H01L21/76264 ,  H01L21/76283

Abstract: The semiconductor device comprises a semiconductor substrate (SB) having locally at least one zone (ZL) terminating in the surface of the substrate and entirely bordered, along its lateral edges and its bottom, by an insulating material so as to be completely isolated from the rest of the substrate. The horizontal isolating layer may be a layer of constant thickness or a crenellated layer.

Abstract translation: 半导体器件包括半导体衬底（SB），其具有局部至少一个区域（ZL），该区域（ZL）终止于衬底的表面，并且沿着其侧边缘及其底部通过绝缘材料整齐地界定，从而与绝缘材料完全隔离 底物的剩余部分。 水平隔离层可以是恒定厚度的层或钝化层。

公开(公告)号：US20020031848A1

公开(公告)日：2002-03-14

申请号：US09898523

申请日：2001-07-03

Applicant: STMicroelectronics S.A.

Inventor： Emmanuel Perrin ,  Herve Jaouen

IPC: H01L021/66 ,  H01L021/302 ,  H01L021/461 ,  G01R031/26

CPC classification number: B24B37/013 ,  B24B37/042 ,  B24B49/03 ,  B24B49/16 ,  H01L21/31053

Abstract: A method of determining the time for polishing the surface of an integrated circuit wafer on a polishing machine. A sample wafer is fabricated to include at least one high plateau and at least one low plateau joined by a sudden transition. At least one initial profile is topographically scanned, and the surface of the sample wafer is polished at a particular polishing pressure for a particular polishing time. The final profile of the polished layer is topographically scanned in the corresponding area, and the initial and final topographical scans of the sample wafer are converted into Fourier series. The surface of the wafer to be polished is topographically scanned, and the topographic scan of the wafer to be polished is converted into a Fourier series. The time for polishing the wafer to be polished is calculated from the Fourier series and the average thickness to be removed.

Abstract translation: 确定在抛光机上抛光集成电路晶片的表面的时间的方法。 制造样品晶片以包括至少一个高平台和至少一个通过突然过渡连接的低平台。 至少一个初始轮廓被地形扫描，并且在特定抛光压力下抛光样品晶片的表面以达到特定的抛光时间。 将抛光层的最终轮廓在相应的区域进行地形扫描，并将样品晶片的初始和最终的地形扫描转换为傅立叶级数。 将待研磨的晶片的表面进行地形扫描，并将要抛光的晶片的地形扫描转换为傅立叶级数。 抛光抛光晶片的时间由傅立叶级数和要去除的平均厚度计算。