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    Schottky-barrier tunneling transistor
    1.
    发明申请
    Schottky-barrier tunneling transistor 失效
    肖特基势垒隧道晶体管

    公开(公告)号：US20040227203A1

    公开(公告)日：2004-11-18

    申请号：US10781383

    申请日：2004-02-18

    发明人： Koucheng Wu

    IPC分类号： H01L031/109 ,  H01L021/28

    CPC分类号： H01L21/84 ,  H01L27/1203

    摘要： A three-terminal semiconductor transistor device comprises a base region formed by a semiconductor material of a first conductivity type at a first concentration, the base region being in contact with a first electrical terminal via a semiconductor material of the second conductivity type at a second concentration, wherein the second concentration is lower than the first concentration. The three-terminal semiconductor transistor device also includes a conductive emitter region in contact with the semiconductor base region, forming a first Schottky barrier junction at the interface of the conductive emitter region and the semiconductor base region. The conductive emitter region is in contact with a second electrical terminal. The three-terminal semiconductor transistor device further includes a conductive collector region in contact with the semiconductor base region, which forms a second Schottky barrier junction at the interface of the conductive collector region and the semiconductor base region. The conductive collector region is in contact with a third electrical terminal. The tunneling current through the first Schottky barrier junction or the second Schottky barrier junction is substantially controlled by the voltage of the semiconductor base region.

    摘要翻译： 三端半导体晶体管器件包括由第一浓度的第一导电类型的半导体材料形成的基极区域，所述基极区域经由第二导电类型的半导体材料以第二浓度与第一电端子接触 ，其中所述第二浓度低于所述第一浓度。 三端子半导体晶体管器件还包括与半导体基底区域接触的导电发射极区域，在导电发射极区域和半导体基底区域的界面处形成第一肖特基势垒结。 导电发射极区域与第二电端子接触。 三端子半导体晶体管器件还包括与半导体基极区域接触的导电集电极区域，其在导电集电极区域和半导体基极区域的界面处形成第二肖特基势垒结。 导电集电极区域与第三电端子接触。 穿过第一肖特基势垒结或第二肖特基势垒结的隧道电流基本上由半导体基极区域的电压控制。

    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step
    2.
    发明申请
    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step 有权
    用于制造存储器件的方法，特别是包括硅化步骤的相变存储器

    公开(公告)号：US20040214415A1

    公开(公告)日：2004-10-28

    申请号：US10758289

    申请日：2004-01-15

    申请人： STMicroelectronics S.r.I. ,  OVONYX Inc.

    发明人： Fabio Pellizzer ,  Roberto Bez ,  Marina Tosi

    IPC分类号： H01L021/28

    CPC分类号： H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    摘要： A process wherein an insulating region is formed in a body at least around an array portion of a semiconductor body; a gate electrode of semiconductor material is formed on top of a circuitry portion of the semiconductor body; a first silicide protection mask is formed on top of the array portion; the gate electrode and the active areas of the circuitry portion are silicided and the first silicide protection mask is removed. The first silicide protection mask (is of polysilicon and is formed simultaneously with the gate electrode. A second silicide protection mask of dielectric material covering the first silicide protection mask is formed before silicidation of the gate electrode. The second silicide protection mask is formed simultaneously with spacers formed laterally to the gate electrode.

    摘要翻译： 一种绝缘区域至少在半导体本体的阵列部分周围形成在主体中的工艺; 半导体材料的栅电极形成在半导体本体的电路部分的顶部; 在阵列部分的顶部形成第一硅化物保护掩模; 栅电极和电路部分的有源区被硅化，并且去除第一硅化物保护掩模。 第一硅化物保护掩模（多晶硅，并与栅电极同时形成）在栅极电极硅化之前形成覆盖第一硅化物保护掩模的第二硅化物保护掩模，第二硅化物保护掩膜与 间隔件横向形成到栅电极。

    Bulk synthesis of metal and metal based dielectric nanowires
    5.
    发明申请
    Bulk synthesis of metal and metal based dielectric nanowires 失效
    金属和金属基介电纳米线的大量合成

    公开(公告)号：US20040132275A1

    公开(公告)日：2004-07-08

    申请号：US10705687

    申请日：2003-11-10

    发明人： Mahendra Kumar Sunkara ,  Hari Chandrasekaran ,  Hongwei Li

    IPC分类号： H01L021/20 ,  H01L021/28 ,  H01L021/44 ,  B32B015/01

    CPC分类号： C22C30/00 ,  C30B11/002 ,  C30B15/10 ,  C30B35/002 ,  Y10T428/12007 ,  Y10T428/12681

    摘要： A process of synthesizing metal and metal nitride nanowires, the steps comprising of: forming a catalytic metal (such as gallium, and indium) on a substrate (such as fused silica quartz, pyrolytic boron nitride, alumina, and sapphire), heating the combination in a pressure chamber, adding gaseous reactant and/or solid metal source, applying sufficient microwave energy (or current in hot filament reactor) to activate the metal of interest (such as gold, copper, tungsten, and bismuth) and continuing the process until nanowires of the desired length are formed. The substrate may be fused silica quartz, the catalytic metal a gallium or indium metal, the gaseous reactant is nitrogen and/or hydrogen and the nanowires are tungsten nitride and/or tungsten.

    摘要翻译： 合成金属和金属氮化物纳米线的方法，其步骤包括：在基底（如熔融石英石英，热解氮化硼，氧化铝和蓝宝石）上形成催化金属（如镓和铟），加热组合 在压力室中加入气体反应物和/或固体金属源，施加足够的微波能量（或热丝反应器中的电流）以激活感兴趣的金属（例如金，铜，钨和铋）并继续该过程直到 形成所需长度的纳米线。 衬底可以是熔融石英石英，催化金属是镓或铟金属，气体反应物是氮和/或氢，并且纳米线是氮化钨和/或钨。

    Method of forming cobalt silicide film and method of manufacturing semiconductor device having cobalt silicide film
    6.
    发明申请
    Method of forming cobalt silicide film and method of manufacturing semiconductor device having cobalt silicide film 失效
    形成硅化钴膜的方法及制造具有硅化钴膜的半导体器件的方法

    公开(公告)号：US20040132268A1

    公开(公告)日：2004-07-08

    申请号：US10686768

    申请日：2003-10-17

    发明人： Kyeong-mo Koo ,  Ja-hum Ku ,  Hye-jeong Park

    IPC分类号： H01L021/28

    CPC分类号： C23C14/5806 ,  C23C14/021 ,  C23C14/165 ,  C23C14/5873 ,  H01L21/28052 ,  H01L29/665

    摘要： A cobalt-containing film on a silicon-containing conductive region, and a titanium-rich capping layer is formed on cobalt-containing film. The atomic % ratio of titanium to other elements (if any) in the titanium-rich capping layer is more than one (1). The resultant structure is annealed so that cobalt of the cobalt-containing film and silicon of the silicon-containing conductive region react with each other to form a cobalt silicide film. When the formation of the cobalt-containing film is carried out at a high temperature, a diffusion restraint interface film is also formed.

    摘要翻译： 在含钴膜上形成含硅导电性区域的含钴膜，富含钛的覆盖层。 富含钛的覆盖层中钛与其他元素（如果有的话）的原子％比大于1（1）。 将所得结构进行退火，使含钴膜的钴和含硅导电区域的硅彼此反应形成硅化钴膜。 当在高温下进行含钴膜的形成时，也形成扩散抑制界面膜。

    Buried digit line stack and process for making same
    7.
    发明申请
    Buried digit line stack and process for making same 有权
    埋地数字线堆栈和进程相同

    公开(公告)号：US20040029371A1

    公开(公告)日：2004-02-12

    申请号：US10636180

    申请日：2003-08-07

    申请人： Micron Technology, Inc.

    发明人： Y. Jeff Hu

    IPC分类号： H01L021/28

    CPC分类号： H01L23/53266 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76867 ,  H01L21/76889 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A process of making a buried digit line stack is disclosed. The process includes forming a silicon-lean metal silicide first film over a polysilicon plug, followed by a silicide compound barrier second film. The silicide compound barrier second film is covered with a refractory metal third film. A salicidation process causes the first film to salicide with the polysilicon plug. In one embodiment, all the aforementioned deposition processes are carried out by physical vapor deposition (nullPVDnull).

    摘要翻译： 公开了一种制作掩埋式数字线叠层的工艺。 该方法包括在多晶硅插塞上形成贫硅金属硅化物第一膜，随后是硅化合物屏障第二膜。 硅化物阻挡层第二膜被难熔金属第三膜覆盖。 水解过程使第一个膜与多晶硅插塞自杀。 在一个实施方案中，所有上述沉积工艺都是通过物理气相沉积（“PVD”）进行的。

    Semiconductor led device and producing method
    8.
    发明申请
    Semiconductor led device and producing method 有权
    半导体led器件及其制造方法

    公开(公告)号：US20040007786A1

    公开(公告)日：2004-01-15

    申请号：US10363432

    申请日：2003-02-28

    发明人： Chang-Tae Kim

    IPC分类号： H01L033/00 ,  H01S005/30 ,  H01L021/28

    CPC分类号： H01L33/44

    摘要： The present invention provides a semiconductor device with InxGa1-xN crystal passivation layer and manufacturing method thereof which effectively blocks the leakage current between the surface & boundary of a device and a pn-junction boundary, and enhances the light emission efficiency as forming new structural semiconductor devices by removing the conventional dielectric passivation layer and using InxGa1-xN crystal layer instead. A semiconductor device with gallium nitride type crystal passivation layer, wherein said semiconductor device has a p-n junction diode construction and forms a InxGa1-xN crystal passivation layer with a specified thickness and a width around the edge of the upper surface of p-GaN layer which is the top layer of the semiconductor device.

    摘要翻译： 本发明提供了具有In x Ga 1-x N晶体钝化层的半导体器件及其制造方法，其有效地阻止器件的表面和边界与pn结边界之间的漏电流，并且在形成新的结构半导体时提高发光效率 通过去除常规介电钝化层并使用In x Ga 1-x N晶体层来代替。 一种具有氮化镓型晶体钝化层的半导体器件，其中所述半导体器件具有pn结二极管结构并形成具有指定厚度和围绕p-GaN层上表面边缘的宽度的In x Ga 1-x N晶体钝化层， 是半导体器件的顶层。

    Article comprising an oxide layer on a GaAs-based semiconductor structure and method of forming same
    9.
    发明申请
    Article comprising an oxide layer on a GaAs-based semiconductor structure and method of forming same 有权
    本发明涉及GaAs基半导体结构上的氧化物层及其形成方法

    公开(公告)号：US20030137018A1

    公开(公告)日：2003-07-24

    申请号：US10051494

    申请日：2002-01-18

    发明人： Matthias Passlack ,  Nicholas William Medendorp JR.

    IPC分类号： H01L021/00 ,  H01L021/28 ,  H01L029/76 ,  H01L029/94

    CPC分类号： H01L29/513 ,  C23C14/08 ,  C30B23/02 ,  C30B29/16 ,  H01L21/02112 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02269 ,  H01L21/28194 ,  H01L21/28264 ,  H01L21/31604 ,  H01L21/31666 ,  H01L29/4232 ,  H01L29/511 ,  H01L29/517

    摘要： A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor structure to form an interface therewith. A second layer of a GanullGd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor, a heterojunction bipolar transistor, or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of GanullGd-oxide. The Ga2O3 layer is used to form a high quality interface with the GaAs-based supporting semiconductor structure while the GanullGd-oxide provides a low oxide leakage current density.

    摘要翻译： 提供了一种化合物半导体结构，其包括具有其上将要形成介电材料的表面的GaAs基支撑半导体结构。 第一层氧化镓位于支撑半导体结构的表面上以与其形成界面。 在第一层上设置第二层Ga-Gd氧化物。 基于GaAs的支撑半导体结构可以是诸如至少部分完成的半导体器件（例如，金属氧化物场效应晶体管，异质结双极晶体管或半导体激光器）的基于GaAs的异质结构。 以这种方式，提供了在氧化物 - GaAs界面处具有低缺陷密度和低氧化物漏电流密度的电介质层结构，因为电介质结构由Ga 2 O 3层，然后由Ga-Gd-氧化物层形成 。 Ga 2 O 3层用于与GaAs基支持半导体结构形成高质量的界面，而Ga-Gd氧化物提供低的氧化物漏电流密度。

    Electrode forming method and field effect transistor
    10.
    发明申请
    Electrode forming method and field effect transistor 有权
    电极形成方法和场效应晶体管

    公开(公告)号：US20030129833A1

    公开(公告)日：2003-07-10

    申请号：US10316210

    申请日：2002-12-10

    申请人： Murata Manufacturing Co., Ltd.

    发明人： Hiroyuki Seto ,  Makoto Inai ,  Hiroyuki Nakano ,  Eiji Tai

    IPC分类号： H01L021/28 ,  H01L021/44 ,  H01L021/4763

    CPC分类号： H01L29/66863 ,  H01L21/0272 ,  H01L21/28587

    摘要： A gate electrode is formed in the following manner. A first resist layer having a first opening is formed on a semiconductor substrate. A second resist layer having a second opening larger than the first opening is formed on the first resist layer. A first conductor layer containing a high-melting-point metal is formed. Subsequently, a second conductor layer containing low-resistance metal is formed, and then the first conductor layer within the second opening is removed by etching. Next, the second resist layer is removed by a lift-off process, and finally the first resist layer is removed by ashing.

    摘要翻译： 以下列方式形成栅电极。 在半导体衬底上形成具有第一开口的第一抗蚀剂层。 在第一抗蚀剂层上形成具有大于第一开口的第二开口的第二抗蚀剂层。 形成含有高熔点金属的第一导体层。 随后，形成包含低电阻金属的第二导体层，然后通过蚀刻去除第二开口内的第一导体层。 接下来，通过剥离处理去除第二抗蚀剂层，最后通过灰化除去第一抗蚀剂层。