Invention Application
US20050014331A1 PROCESS FOR PLANARIZING ARRAY TOP OXIDE IN VERTICAL MOSFET DRAM ARRAYS
有权
在垂直MOSFET DRAM阵列中平面排列顶部氧化物的方法
- Patent Title: PROCESS FOR PLANARIZING ARRAY TOP OXIDE IN VERTICAL MOSFET DRAM ARRAYS
- Patent Title (中): 在垂直MOSFET DRAM阵列中平面排列顶部氧化物的方法
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Application No.: US10604361Application Date: 2003-07-14
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Publication No.: US20050014331A1Publication Date: 2005-01-20
- Inventor: Sheng-Wei Yang , Cheng-Chih Huang , Chien-Mao Liao
- Applicant: Sheng-Wei Yang , Cheng-Chih Huang , Chien-Mao Liao
- Main IPC: H01L21/3105
- IPC: H01L21/3105 ; H01L21/311 ; H01L21/316 ; H01L21/8242 ; H01L21/8234
Abstract:
The present invention provides a process for planarizing array top oxide (ATO) in vertical MOSFET DRAM arrays. In contrast to the prior art ARC-RIE planarization method for EA/ES (etch array/etch support) module, the present invention takes advantage of chemical mechanical polishing (CMP) technique to overcome residue problems that used to occur at the transition region or array edge. It might cause capacitor device failure when ATO residue is left on the transition region.
Public/Granted literature
- US06897108B2 Process for planarizing array top oxide in vertical MOSFET DRAM arrays Public/Granted day:2005-05-24
Information query
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