发明申请
- 专利标题: Method of manufacturing semiconductor device
- 专利标题(中): 制造半导体器件的方法
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申请号: US10940820申请日: 2004-09-15
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公开(公告)号: US20050064699A1公开(公告)日: 2005-03-24
- 发明人: Seiichi Kondo , Kaori Misawa , Shunichi Tokitoh , Takashi Nasuno
- 申请人: Seiichi Kondo , Kaori Misawa , Shunichi Tokitoh , Takashi Nasuno
- 申请人地址: JP Tsukuba-shi
- 专利权人: Semiconductor Leading Edge Technologies, Inc.
- 当前专利权人: Semiconductor Leading Edge Technologies, Inc.
- 当前专利权人地址: JP Tsukuba-shi
- 优先权: JP2003-326559 20030918; JP2003-326560 20030918
- 主分类号: H01L27/00
- IPC分类号: H01L27/00 ; H01L21/28 ; H01L21/312 ; H01L21/314 ; H01L21/316 ; H01L21/318 ; H01L21/768 ; H01L21/4763 ; H01L21/44
摘要:
A first CVD dielectric layer is deposited on a surface of a semiconductor substrate. Next, low-k layers are deposited in at least two different steps to form one of a via-layer dielectric film and a wiring-layer dielectric film on the first CVD dielectric layer. Immediately after the depositions, thermal treatment is performed. A second CVD dielectric layer is deposited on the low-k layers. A groove is formed in the second CVD dielectric layer and the low-k layers. A metal layer is deposited on that structure, filling the groove. The metal layer is removed from the second CVD dielectric layer by chemical mechanical polishing.
公开/授权文献
- US07125794B2 Method of manufacturing semiconductor device 公开/授权日:2006-10-24
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