The digital electronic circuit (1) comprises a logic cell (2) for processing data (82), a flip-flop (3) for storing data (83) processed in the logic cell (2), a power supply (4), and a clock (5) for triggering the flip-flop (3). The logic cell (2) is disconnected from the power supply (4) when the clock (5) is not active, as it is not needed for memorizing of the flip-flop states, and connected with the power supply (4) when the clock (5) is enabled. For switching the power supply, a switch (7) switched by the clock enable (6) is arranged between the logic cell (2) and the power supply (4). Such a simple additional switch (7) occupies only a relatively small area on the chip, but permits a drastic reduction by about 90% of the leakage currents. The circuit (1) is especially suitable for a decimation of leakage currents in sub-micron process design and may be used for instance in mobile telecommunication devices.