发明申请
- 专利标题: Integration of high k gate dielectric
- 专利标题(中): 高k栅介质的集成
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申请号: US11148721申请日: 2005-06-09
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公开(公告)号: US20050233529A1公开(公告)日: 2005-10-20
- 发明人: Christophe Pomarede , Michael Givens , Eric Shero , Michael Todd
- 申请人: Christophe Pomarede , Michael Givens , Eric Shero , Michael Todd
- 主分类号: C23C16/24
- IPC分类号: C23C16/24 ; C23C16/02 ; C30B25/02 ; H01L21/20 ; H01L21/205 ; H01L21/28 ; H01L21/285 ; H01L21/3205 ; H01L21/336 ; H01L21/4763 ; H01L21/8242 ; H01L27/108 ; H01L29/423 ; H01L29/49 ; H01L29/51 ; H01L29/78 ; H01L29/786 ; H01L31/18 ; H01L31/20
摘要:
Methods are provided herein for forming electrode layers over high dielectric constant (“high k”) materials. In the illustrated embodiments, a high k gate dielectric, such as zirconium oxide, is protected from reduction during a subsequent deposition of silicon-containing gate electrode. In particular, a seed deposition phase includes conditions designed for minimizing hydrogen reduction of the gate dielectric, including low hydrogen content, low temperatures and/or low partial pressures of the silicon source gas. Conditions are preferably changed for higher deposition rates and deposition continues in a bulk phase. Desirably, though, hydrogen diffusion is still minimized by controlling the above-noted parameters. In one embodiment, high k dielectric reduction is minimized through omission of a hydrogen carrier gas. In another embodiment, higher order silanes, aid in reducing hydrogen content for a given deposition rate.
公开/授权文献
- US07790556B2 Integration of high k gate dielectric 公开/授权日:2010-09-07