Disclosed herein is a dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells provided on both sides with the sense amplifier array as the center are connected to one another while circuit connections in the sense amplifier array are being ensured by wiring means using the common electrodes.,