公开(公告)号：US20070297257A1

公开(公告)日：2007-12-27

申请号：US11889902

申请日：2007-08-17

申请人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

发明人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

IPC分类号： G11C7/02

CPC分类号： G11C7/02 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4074 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10897

摘要： A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of the capacitor and a capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells, and a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs placed so as to extend in directions opposite to each other from each pair of input/output terminals. Power supply lines are provided in mesh form inclusive of a portion above word drivers.

摘要翻译： 动态RAM包含多个动态存储单元，每个动态存储单元包括具有作为选择端子的栅极集合的MOSFET，作为输入/输出端子的一个源极和漏极组，以及连接到电容器的存储节点的另一个源极和漏极 以及电容器，分别连接到多个动态存储单元的选择端子的多个字线，分别连接到多个动态存储单元的输入/输出端子的多个互补位线对，以及读出放大器 阵列包括多个锁存电路，其分别放大互补位线对之间的电压差，以便从每对输入/输出端子彼此相反的方向延伸。 电源线以网格形式提供，包括字驱动器上方的一部分。

公开(公告)号：US06944080B2

公开(公告)日：2005-09-13

申请号：US10938794

申请日：2004-09-13

申请人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

发明人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C5/06 ,  G11C7/02 ,  G11C7/18 ,  G11C8/00 ,  G11C11/34 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC分类号： G11C7/02 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4074 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10897

摘要： A dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells, on both sides with the sense amplifier array as the center are connected to one another while circuit connections in the sense amplifier array are being ensured by wiring using the common electrodes.

摘要翻译： 一种动态RAM，包括分别连接到多个动态存储单元的地址选择端的多个字线，分别连接到所述多个动态存储单元的输入/输出端的多个互补位线对，并且被放置在与 以及根据操作定时信号提供工作电压的读出放大器阵列，并且包括用于分别放大互补位线对之间的电压差的多个锁存电路。 在动态RAM中，与以感测放大器阵列为中心的两侧的多个动态存储单元的地址选择MOSFET和信息存储电容器之间的连接点对应的存储节点提供的公共电极彼此连接 而通过使用公共电极的布线来确保读出放大器阵列中的电路连接。

公开(公告)号：US06807120B2

公开(公告)日：2004-10-19

申请号：US10309180

申请日：2002-12-04

申请人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

发明人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

IPC分类号： G11C702

CPC分类号： G11C7/02 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4074 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10897

摘要： A semiconductor device includes a first region having first bit lines, first word lines and first memory cells; a second region having second bit lines, second word lines and second memory cells; a third region having sense amplifiers placed between the first region and the second region; a first conductive layer being over the first region; a second conductive layer being over the second region; and a connecting layer, being over the third region, which electrically connects the first conductive layer with the second conductive layer. The sense amplifiers amplify differences in voltage between the first bit lines and the second bit lines. Each of the first memory cells includes a first storage capacitor having an electrode connected to the first conductive layer. Each of the second memory cells includes a second storage capacitor having an electrode connected to the second conductive layer.

摘要翻译： 半导体器件包括具有第一位线，第一字线和第一存储器单元的第一区域; 具有第二位线的第二区域，第二字线和第二存储器单元; 具有放置在所述第一区域和所述第二区域之间的读出放大器的第三区域; 在所述第一区域之上的第一导电层; 在所述第二区域上方的第二导电层; 以及连接层，其在第三区域之上，其将第一导电层与第二导电层电连接。 感测放大器放大第一位线和第二位线之间的电压差。 每个第一存储单元包括具有连接到第一导电层的电极的第一存储电容器。 每个第二存储单元包括具有连接到第二导电层的电极的第二存储电容器。

公开(公告)号：US20050270889A1

公开(公告)日：2005-12-08

申请号：US11198357

申请日：2005-08-08

申请人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

发明人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C5/06 ,  G11C7/02 ,  G11C7/18 ,  G11C8/00 ,  G11C11/34 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC分类号： G11C7/02 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4074 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10897

摘要： Disclosed herein is a dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells provided on both sides with the sense amplifier array as the center are connected to one another while circuit connections in the sense amplifier array are being ensured by wiring means using the common electrodes.,

摘要翻译： 这里公开了一种动态RAM，其包括分别连接到多个动态存储单元的地址选择端的多个字线，分别连接到多个动态存储单元的输入/输出端并放置在多个动态存储单元中的多个互补位线对 方向相反，以及根据操作定时信号被提供有工作电压的读出放大器阵列，并且包括用于分别放大互补位线对之间的电压差的多个锁存电路。 在动态RAM中，以与感测放大器阵列为中心的两侧设置的多个动态存储单元的地址选择MOSFET和信息存储电容器之间的连接点对应的存储节点提供的公共电极彼此连接 而通过使用公共电极的布线装置来确保读出放大器阵列中的电路连接，

公开(公告)号：US20050030783A1

公开(公告)日：2005-02-10

申请号：US10938794

申请日：2004-09-13

申请人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

发明人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C5/06 ,  G11C7/02 ,  G11C7/18 ,  G11C8/00 ,  G11C11/34 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  G11C11/22

CPC分类号： G11C7/02 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4074 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10897

摘要： Disclosed herein is a dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells provided on both sides with the sense amplifier array as the center are connected to one another while circuit connections in the sense amplifier array are being ensured by wiring means using the common electrodes.

摘要翻译： 这里公开了一种动态RAM，其包括分别连接到多个动态存储单元的地址选择端的多个字线，分别连接到多个动态存储单元的输入/输出端并放置在多个动态存储单元中的多个互补位线对 方向相反，以及根据操作定时信号被提供有工作电压的读出放大器阵列，并且包括用于分别放大互补位线对之间的电压差的多个锁存电路。 在动态RAM中，以与感测放大器阵列为中心的两侧设置的多个动态存储单元的地址选择MOSFET和信息存储电容器之间的连接点对应的存储节点提供的公共电极彼此连接 而通过使用公共电极的布线装置来确保读出放大器阵列中的电路连接。

公开(公告)号：US07274613B2

公开(公告)日：2007-09-25

申请号：US11198357

申请日：2005-08-08

申请人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

发明人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

IPC分类号： G11C7/02

CPC分类号： G11C7/02 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4074 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10897

摘要： A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of a capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells, and a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs placed so as to extend in directions opposite to each other from each pair of input/output terminals. Power supply lines are provided in mesh form inclusive of a portion above word drivers.

摘要翻译： 动态RAM包含多个动态存储单元，每个动态存储单元包括一个MOSFET，其栅极设置为选择端子，一个源极和漏极组作为输入/输出端子，另一个源极和漏极连接到电容器的存储节点 分别连接到多个动态存储单元的选择端的多个字线，分别连接到多个动态存储单元的输入/输出端的多个互补位线对，以及一个读出放大器阵列，包括一个 多个锁存电路分别放大互补位线对之间的电压差，以便从每对输入/输出端子彼此相反的方向延伸。 电源线以网格形式提供，包括字驱动器上方的一部分。

公开(公告)号：US06501672B1

公开(公告)日：2002-12-31

申请号：US09656477

申请日：2000-09-06

申请人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

发明人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

IPC分类号： G11C506

CPC分类号： G11C7/02 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4074 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10897

摘要： A dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided, in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells, on both sides of the sense amplifier array are connected to one another by wiring using the common electrodes.

摘要翻译： 一种动态RAM，包括分别连接到多个动态存储单元的地址选择端的多个字线，分别连接到所述多个动态存储单元的输入/输出端的多个互补位线对，并且被放置在与 以及根据操作定时信号提供工作电压的读出放大器阵列，并且包括用于分别放大互补位线对之间的电压差的多个锁存电路。 在动态RAM中，与读出放大器阵列两侧的地址选择用MOSFET和多个动态存储单元的信息存储电容之间的连接点对应的存储节点相对设置的公共电极通过布线 使用公共电极。

公开(公告)号：US06756262B1

公开(公告)日：2004-06-29

申请号：US09708450

申请日：2000-11-09

申请人： Yoshitaka Nakamura ,  Isamu Asano ,  Satoru Yamada ,  Tsugio Takahashi ,  Yuzuru Ohji ,  Masayoshi Hirasawa ,  Takashi Yunogami ,  Tomonori Sekiguchi

发明人： Yoshitaka Nakamura ,  Isamu Asano ,  Satoru Yamada ,  Tsugio Takahashi ,  Yuzuru Ohji ,  Masayoshi Hirasawa ,  Takashi Yunogami ,  Tomonori Sekiguchi

IPC分类号： H01L218249

CPC分类号： H01L28/75 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10894 ,  H01L28/55 ,  H01L28/65 ,  H01L28/90

摘要： Conduction reliability between a capacitor upper electrode and a plug connected to an upper layer wire is kept high to prevent connection defects and to reduce the resistance of the capacitor upper electrode. In a capacitor of a DRAM comprising a lower electrode 45 made of ruthenium, a capacitor insulating film 50 made of BST and an upper electrode 49, the upper electrode 49 has a laminate structure comprising a ruthenium film 47 formed on the side of the capacitor insulating film 50 and a tungsten film 48 formed over the former.

摘要翻译： 电容器上部电极和连接到上层电线的插头之间的传导可靠性保持较高，以防止连接缺陷并降低电容器上部电极的电阻。 在包括由钌制成的下电极45的电容器，由BST制成的电容器绝缘膜50和上电极49的情况​​下，上电极49具有包括形成在绝缘电容器侧的钌膜47的层叠结构 膜50和形成在前者上的钨膜48。

公开(公告)号：US09314041B2

公开(公告)日：2016-04-19

申请号：US11817617

申请日：2006-02-23

申请人： Toshihiro Sashihara ,  Makoto Yamaguchi ,  Yoshitaka Nakamura ,  Shuji Ikegami ,  Seiko Narushima ,  Katsunori Kimura ,  Shinya Nagafuchi ,  Masaki Terahara

发明人： Toshihiro Sashihara ,  Makoto Yamaguchi ,  Yoshitaka Nakamura ,  Shuji Ikegami ,  Seiko Narushima ,  Katsunori Kimura ,  Shinya Nagafuchi ,  Masaki Terahara

IPC分类号： C12N1/20 ,  A23C19/032 ,  A23C9/123 ,  A23L1/30 ,  A61K35/747 ,  C12R1/225

CPC分类号： A23C19/0323 ,  A23C9/1234 ,  A23L33/135 ,  A61K35/747 ,  C12R1/225

摘要： A probiotic lactobacillus was discovered from lactobacilli of the Lactobacillus genus independently isolated from human adult feces. The probiotic lactobacillus was selected from other bacterial strains for: (1) being highly resistant to gastric acid/bile acid; (2) having a high promoting activity on IL-12 production from mouse derived spleen cells and a high Th1/Th2 balance-improving effect; (3) having a high ability to inhibit the production of antigen-specific IgE induced by intraperitoneally administering ovalbumin to BALB/c mice; (4) having a high ability to inhibit the production of antigen-specific IgE induced by orally administering a food antigen to C57BL/6N mice; (5) having a high Natural Killer cell-activating ability; (6) having a high IL-12 production-promoting activity on spleen cells and mesenteric lymph node cells derived from mice immunized with ovalbumin and a high Th1/Th2 balance-improving effect; and (7) having a high ability to suppress eosinophilia induced by a cedar pollen-extracted antigen. This discovery led to the completion of the present invention.

摘要翻译： 从人类成年粪便独立分离的乳杆菌属的乳杆菌中发现益生菌乳杆菌。 选自其他细菌菌株的益生菌乳杆菌：（1）对胃酸/胆汁酸具有高度抗性; （2）对小鼠来源的脾细胞的IL-12产生促进活性高，Th1 / Th2平衡提高效果好; （3）具有抑制通过向BALB / c小鼠腹膜内给予卵白蛋白诱导的抗原特异性IgE产生的高能力; （4）通过口服给C57BL / 6N小鼠口服给予抗原而诱导抗原特异性IgE产生的能力较强; （5）具有高自然杀伤细胞活化能力; （6）对来自用卵白蛋白免疫的小鼠脾细胞和肠系膜淋巴结细胞具有高IL-12产生促进活性和高Th1 / Th2平衡改善效果; 和（7）具有高的抑制由雪松花粉提取的抗原诱导的嗜酸性粒细胞增多的能力。 这一发现导致了本发明的完成。

公开(公告)号：US20130336841A1

公开(公告)日：2013-12-19

申请号：US14002894

申请日：2011-03-03

申请人： Yoshitaka Nakamura ,  Hirotaka Saito ,  Toru Kidokoro ,  Hiroshi Sawada ,  Kenji Sakurai

发明人： Yoshitaka Nakamura ,  Hirotaka Saito ,  Toru Kidokoro ,  Hiroshi Sawada ,  Kenji Sakurai

IPC分类号： G01N33/00

CPC分类号： G01N33/0054 ,  F01N3/206 ,  F01N11/007 ,  F01N2550/02 ,  F01N2560/021 ,  F01N2610/03 ,  F01N2900/0408 ,  F01N2900/1402 ,  Y02T10/47

摘要： The determination of deterioration of a NOx storage reduction catalyst (4) is carried out more accurately. When a reducing agent is supplied from a supply device (5) to the NOx catalyst (4), a first supply of the reducing agent and a second supply of the reducing agent are carried out in a sequential manner by adjusting an amount of the reducing agent in such a manner that an air fuel ratio of the exhaust gas becomes a predetermined rich air fuel ratio, and a determination whether or not the NOx catalyst (4) has deteriorated is made based on a detected value of a detection device (8), which detects NH3 in the exhaust gas at the downstream side of the NOx catalyst (4), after a predetermined period of time has elapsed from the start of the first supply of the reducing agent, and after the start of the second supply of the reducing agent.

摘要翻译： 进一步精确地确定NOx储存还原催化剂（4）的劣化。 当从供给装置（5）向NOx催化剂（4）供给还原剂时，通过调节还原剂的量来顺序地进行还原剂的第一次供给和还原剂的第二供给 以使得排气的空燃比成为规定的浓空燃比，并且基于检测装置（8）的检测值来判定NOx催化剂（4）是否劣化， ，其在从所述还原剂的第一次供给开始经过预定时间后，在所述NOx催化剂（4）的下游侧的废气中检测NH 3，并且在所述第二次供给所述NOx催化剂 还原剂。