发明申请
- 专利标题： Recessed gate electrodes having covered layer interfaces and methods of forming the same
- 专利标题（中）： 具有覆盖层界面的嵌入式栅电极及其形成方法
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申请号： US11144142申请日： 2005-06-03
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公开(公告)号： US20050272233A1公开(公告)日： 2005-12-08
- 发明人: Byung-Hak Lee , Chang-Won Lee , Hee-Sook Park , Woong-Hee Sohn , Sun-Pil Youn , Jong-ryeol Yoo
- 申请人： Byung-Hak Lee , Chang-Won Lee , Hee-Sook Park , Woong-Hee Sohn , Sun-Pil Youn , Jong-ryeol Yoo
- 优先权： KR2004-40990 20040604; KR2005-04616 20050118
- 主分类号： H01L21/28
- IPC分类号： H01L21/28 ; H01L21/3205 ; H01L21/336 ; H01L21/4763 ; H01L21/76 ; H01L21/8234 ; H01L21/8242 ; H01L27/148 ; H01L29/51 ; H01L29/768 ; H01L29/78
摘要：
A gate electrode of a transistor can include an interface between a polysilicon conformal layer and a tungsten layer thereon in a trench in a substrate and a capping layer extending across the trench and covering the interface. Related methods are also disclosed.
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