发明申请
- 专利标题： PACKAGE STRUCTURE AND METHOD FOR REDUCING DIELECTRIC LAYER DELAMINATION
- 专利标题（中）： 用于减少介质层分层的包装结构和方法
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申请号： US12757440申请日： 2010-04-09
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公开(公告)号： US20110018128A1公开(公告)日： 2011-01-27
- 发明人: Hsiu-Ping WEI , Shin-Puu JENG , Hao-Yi TSAI , Hsien-Wei CHEN , Yu-Wen LIU , Ying-Ju CHEN , Tzuan-Horng LIU
- 申请人： Hsiu-Ping WEI , Shin-Puu JENG , Hao-Yi TSAI , Hsien-Wei CHEN , Yu-Wen LIU , Ying-Ju CHEN , Tzuan-Horng LIU
- 申请人地址： TW Hsinchu
- 专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人地址： TW Hsinchu
- 主分类号： H01L23/498
- IPC分类号： H01L23/498 ; H01L21/3205
摘要：
A semiconductor package structure is provided. The structure includes a semiconductor chip having a plurality of interconnect layers formed thereover. A first passivation layer is formed over the plurality of interconnect layers. A stress buffer layer is formed over the first passivation layer. A bonding pad is formed over the stress buffer layer. A second passivation layer is formed over a portion of the bonding pad, the second passivation having at least one opening therein exposing a portion of the bonding pad.