公开(公告)号：US09138422B2

公开(公告)日：2015-09-22

申请号：US14058066

申请日：2013-10-18

申请人： Chi-Ying F. Huang ,  Chi-Tai Yeh ,  Chun-Hung Wu ,  Yu-Wen Liu

发明人： Chi-Ying F. Huang ,  Chi-Tai Yeh ,  Chun-Hung Wu ,  Yu-Wen Liu

IPC分类号： A61K31/365 ,  A61K31/5377 ,  A61K45/06 ,  A61K31/517

CPC分类号： A61K31/365 ,  A61K31/517 ,  A61K31/5377 ,  A61K45/06 ,  A61K2300/00

摘要： The present invention provides a method for inhibiting the growth of cancer stem cells, particularly colorectal cancer stem cells, liver cancer stem cells, lung cancer stem cells or breast cancer stem cells, comprising administering to a subject in need thereof a therapeutically effective amount of a compound of antimycin A or a pharmaceutically acceptable salt thereof, together with a pharmaceutically acceptable carrier.

摘要翻译： 本发明提供了抑制癌症干细胞，特别是结肠直肠癌干细胞，肝癌干细胞，肺癌干细胞或乳腺癌干细胞的生长的方法，其包括向有需要的受试者施用治疗有效量的 抗霉素A或其药学上可接受的盐与药学上可接受的载体的化合物。

公开(公告)号：US08860208B2

公开(公告)日：2014-10-14

申请号：US13023151

申请日：2011-02-08

申请人： Hsien-Wei Chen ,  Yu-Wen Liu ,  Jyh-Cherng Sheu ,  Hao-Yi Tsai ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Shang-Yun Hou

发明人： Hsien-Wei Chen ,  Yu-Wen Liu ,  Jyh-Cherng Sheu ,  Hao-Yi Tsai ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Shang-Yun Hou

IPC分类号： H01L23/34 ,  H01L23/58 ,  H01L21/78 ,  H01L23/367 ,  B23K26/36 ,  B23K26/40 ,  H01L21/66

CPC分类号： H01L23/3677 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  H01L21/78 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a first chip including a first edge; and a second chip having a second edge facing the first edge. A scribe line is between and adjoining the first edge and the second edge. A heat spreader includes a portion in the scribe line, wherein the heat spreader includes a plurality of vias and a plurality of metal lines. The portion of the heat spreader in the scribe line has a second length at least close to, or greater than, a first length of the first edge.

摘要翻译： 集成电路结构包括：第一芯片，包括第一边缘; 以及具有面向第一边缘的第二边缘的第二芯片。 划线在第一边缘和第二边缘之间并相邻。 散热器包括划线中的一部分，其中散热器包括多个通孔和多个金属线。 散热器在划线中的部分具有至少接近或大于第一边缘的第一长度的第二长度。

公开(公告)号：US08648444B2

公开(公告)日：2014-02-11

申请号：US12054082

申请日：2008-03-24

申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Shin-Puu Jeng ,  Yu-Wen Liu

发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Shin-Puu Jeng ,  Yu-Wen Liu

IPC分类号： H01L21/78

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring layers have at least one metal film structures substantially covering corner regions where two scribe lines intersect to inhibit delamination at the USG/ELK interface during wafer dicing operation.

摘要翻译： 公开了具有多层布线结构的半导体晶片。 晶片包括排列在晶片上的多个芯片管芯区域和在芯片管芯区域之间的划线区域。 具有在ELK布线层之上的USG顶层布线层的半导体晶片的划线具有至少一个金属膜结构，其基本上覆盖两个划线相交的拐角区域，以在晶片切割操作期间在USG / ELK界面处抑制分层。

公开(公告)号：US20130302020A1

公开(公告)日：2013-11-14

申请号：US13467124

申请日：2012-05-09

申请人： Hun-Hung LU ,  Yu-Wen Liu

发明人： Hun-Hung LU ,  Yu-Wen Liu

IPC分类号： F24H1/18

CPC分类号： F24H9/1818 ,  F24H1/121 ,  F24H9/0015 ,  F24H2250/02 ,  H05B3/12 ,  H05B3/262 ,  H05B3/44 ,  H05B2203/003 ,  H05B2203/014

摘要： A heating device for an electric water heater, especially a heating device that can effectively recover waste heat, the device includes a secondary water box provided on one of the top and the bottom sides of a flat type main water box, the secondary water box is communicated with the main water box to guide water of the secondary water box into the main water box; the main and the secondary water boxes are provided therebetween with a laminate electric heating board of which the top and the bottom sides are clung respectively to the secondary water box and the main water box, an effect of preheating the water in the secondary water box is obtained to thereby effectively use the waste heat for saving energy source, and heating efficiency can be increased.

摘要翻译： 一种用于电热水器的加热装置，特别是能够有效回收废热的加热装置，该装置包括设置在平板式主水箱的顶侧和底侧之一的二次水箱，次水箱为 与主水箱通信，将二次水箱的水引导到主水箱; 主水箱和二次水箱之间设置有层压电加热板，其顶侧和底侧分别紧固在二次水箱和主水箱上，预热二次水箱中的水的效果为 从而有效地利用废热来节约能源，并且可以提高加热效率。

公开(公告)号：US08298838B2

公开(公告)日：2012-10-30

申请号：US12712133

申请日：2010-02-24

申请人： Po-Fu Chou ,  Yu-Wen Liu

发明人： Po-Fu Chou ,  Yu-Wen Liu

IPC分类号： G01R31/26 ,  H01L21/66

CPC分类号： H01L22/24

摘要： A method for staining a sample includes the following steps. A test device is provided. The test device is sampled to obtain a sample. The sample includes a substrate, an active area disposed within the substrate and having a first doped substrate region and a second doped substrate region, at least one gate disposed between the first doped substrate region and the second doped substrate region, and an exposed shallow trench isolation embedded in the substrate and surrounding the active area. A first staining procedure is then carried out to selectively remove the shallow trench isolation to form a first void and to entirely expose the active area. A second staining procedure is subsequently carried out to selectively stain the first doped substrate region and the second doped substrate region to form a second void.

摘要翻译： 染色样品的方法包括以下步骤。 提供测试设备。 对测试装置进行采样以获得样品。 样品包括衬底，设置在衬底内并具有第一掺杂衬底区域和第二掺杂衬底区域的有源区域，设置在第一掺杂衬底区域和第二掺杂衬底区域之间的至少一个栅极和暴露的浅沟槽 隔离嵌入基板并围绕有源区域。 然后执行第一染色程序以选择性地去除浅沟槽隔离以形成第一空隙并且完全暴露活性区域。 随后执行第二染色程序以选择性地污染第一掺杂衬底区域和第二掺杂衬底区域以形成第二空隙。

公开(公告)号：US20120261662A1

公开(公告)日：2012-10-18

申请号：US13085745

申请日：2011-04-13

申请人： Shih-Wei LIANG ,  Yu-Wen LIU ,  Hsien-Wei CHEN

发明人： Shih-Wei LIANG ,  Yu-Wen LIU ,  Hsien-Wei CHEN

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L22/34 ,  H01L23/522 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05096 ,  H01L2224/05572 ,  H01L2224/14131 ,  H01L2224/14179 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2224/05552

摘要： An integrated circuit system comprising a first integrated and at least one of a second integrated circuit, interposer or printed circuit board. The first integrated circuit further comprising a wiring stack, bond pads electrically connected to the wiring stack, and bump balls formed on the bond pads. First portions of the wiring stack and the bond pads form a functional circuit, and second portions of the wiring stack and the bond pads form a test circuit. A portion of the bump balls comprising dummy bump balls. The dummy bump balls electrically connected to the second portions of the wiring stack and the bond pads. The at least one of the second integrated circuit, interposer orprinted circuit board forming a portion of the test circuit.

摘要翻译： 一种集成电路系统，包括第一集成电路和第二集成电路，插入器或印刷电路板中的至少一个。 第一集成电路还包括布线堆叠，电连接到布线堆叠的接合焊盘以及形成在接合焊盘上的凸块球。 布线堆叠和接合焊盘的第一部分形成功能电路，并且布线堆叠和接合焊盘的第二部分形成测试电路。 凸块球的一部分包括虚拟凸块球。 虚拟凸块球电连接到布线堆叠的第二部分和接合垫。 形成测试电路的一部分的第二集成电路，插入器或印刷电路板中的至少一个。

公开(公告)号：US08227916B2

公开(公告)日：2012-07-24

申请号：US12757440

申请日：2010-04-09

申请人： Hsiu-Ping Wei ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Yu-Wen Liu ,  Ying-Ju Chen ,  Tzuan-Horng Liu

发明人： Hsiu-Ping Wei ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Yu-Wen Liu ,  Ying-Ju Chen ,  Tzuan-Horng Liu

IPC分类号： H01L23/498 ,  H01L21/3205

CPC分类号： H01L21/76801 ,  H01L23/3192 ,  H01L23/522 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor package structure is provided. The structure includes a semiconductor chip having a plurality of interconnect layers formed thereover. A first passivation layer is formed over the plurality of interconnect layers. A stress buffer layer is formed over the first passivation layer. A bonding pad is formed over the stress buffer layer. A second passivation layer is formed over a portion of the bonding pad, the second passivation having at least one opening therein exposing a portion of the bonding pad.

摘要翻译： 提供半导体封装结构。 该结构包括其上形成有多个互连层的半导体芯片。 在多个互连层上形成第一钝化层。 在第一钝化层上形成应力缓冲层。 在应力缓冲层上形成接合焊盘。 在接合焊盘的一部分上形成第二钝化层，第二钝化层具有至少一个开口，露出焊接区的一部分。

公开(公告)号：US20120175728A1

公开(公告)日：2012-07-12

申请号：US13004261

申请日：2011-01-11

申请人： Ching-Jung YANG ,  Yu-Wen LIU ,  Michael Shou-Ming TONG ,  Hsien-Wei CHEN ,  Chung-Ying YANG ,  Tsung-Yuan YU

发明人： Ching-Jung YANG ,  Yu-Wen LIU ,  Michael Shou-Ming TONG ,  Hsien-Wei CHEN ,  Chung-Ying YANG ,  Tsung-Yuan YU

IPC分类号： H01L23/00 ,  H01L21/31

CPC分类号： H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate having a circuit region and a seal ring region. The seal ring region surrounds the circuit region. A seal ring structure is disposed over the seal ring region. The seal ring structure has a first portion and a second portion above the first portion. The first portion has a width W1, and the second portion has a width W2. The width W1 is less than the width W2.

摘要翻译： 半导体器件包括具有电路区域和密封环区域的衬底。 密封圈区域围绕电路区域。 密封环结构设置在密封环区域的上方。 密封环结构具有在第一部分上方的第一部分和第二部分。 第一部分具有宽度W1，第二部分具有宽度W2。 宽度W1小于宽度W2。

公开(公告)号：US20100252916A1

公开(公告)日：2010-10-07

申请号：US12417394

申请日：2009-04-02

申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Shin-Puu Jeng

发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Shin-Puu Jeng

IPC分类号： H01L23/544

CPC分类号： H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided that includes a semiconductor substrate, a plurality of dies formed on the semiconductor substrate, the plurality of dies being separated from one another by a first region extending along a first direction and a second region extending along a second direction different from the first direction, a dummy metal structure formed within a third region that includes a region defined by an intersection of the first region and the second region, a plurality of metal interconnection layers formed over the substrate, and a plurality of dielectric layers formed over the substrate. Each of the metal interconnection layers is disposed within each of the dielectric layers and a dielectric constant of at least one of the dielectric layers is less than about 2.6.

摘要翻译： 提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底上的多个管芯，所述多个管芯沿着第一方向延伸的第一区域彼此分离，并且沿着不同于第二方向的第二方向延伸的第二区域 第一方向，形成在第三区域内的虚设金属结构，所述第三区域包括由所述第一区域和所述第二区域的交点限定的区域，形成在所述基板上的多个金属互连层，以及形成在所述第二区域上的多个电介质层 基质。 每个金属互连层设置在每个介电层内，并且至少一个电介质层的介电常数小于约2.6。

公开(公告)号：US20100123246A1

公开(公告)日：2010-05-20

申请号：US12272501

申请日：2008-11-17

申请人： Hsien-Wei Chen ,  Yu-Wen Liu ,  Hao-Yi Tsai ,  Shin-Puu Jeng ,  Ying-Ju Chen

发明人： Hsien-Wei Chen ,  Yu-Wen Liu ,  Hao-Yi Tsai ,  Shin-Puu Jeng ,  Ying-Ju Chen

IPC分类号： H01L23/488

CPC分类号： H01L24/03 ,  H01L23/3192 ,  H01L23/585 ,  H01L24/05 ,  H01L24/08 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48684 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48784 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48744

摘要： An integrated circuit structure includes a bond pad; an Mtop pad located directly underlying the bond pad; an Mtop-1 pad having at least a portion directly underlying the Mtop pad, wherein at least one of the Mtop pad and the Mtop-1 pad has a horizontal dimension smaller than a horizontal dimension of the bond pad; a plurality of vias interconnecting the Mtop pad and the Mtop-1 pad; and a bond ball on the bond pad. Each of the Mtop pad and the Mtop-1 pad has positive enclosures to the bond ball in all horizontal directions.

摘要翻译： 集成电路结构包括接合焊盘; 直接位于接合垫下面的Mtop垫; Mtop-1垫具有直接位于Mtop垫下方的至少一部分，其中Mtop垫和Mtop-1垫中的至少一个具有小于接合垫的水平尺寸的水平尺寸; 将Mtop焊盘和Mtop-1焊盘互连的多个通孔; 和粘结垫上的粘结球。 每个Mtop垫和Mtop-1垫在所有水平方向上都具有粘结球的正面外壳。