Invention Application
- Patent Title: ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
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Application No.: US14553521Application Date: 2014-11-25
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Publication No.: US20160149013A1Publication Date: 2016-05-26
- Inventor: Anthony I. CHOU , Arvind KUMAR , Chung-Hsun LIN , Shreesh NARASIMHA , Claude ORTOLLAND , Jonathan T. SHAW
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Main IPC: H01L29/51
- IPC: H01L29/51 ; H01L21/02 ; H01L21/28 ; H01L29/423 ; H01L21/265 ; H01L29/66

Abstract:
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
Public/Granted literature
- US09412667B2 Asymmetric high-k dielectric for reducing gate induced drain leakage Public/Granted day:2016-08-09
Information query
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