公开(公告)号：US20190147952A1

公开(公告)日：2019-05-16

申请号：US16243574

申请日：2019-01-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor ARSOVSKI ,  Suparna BHATTACHARYA ,  Arvind KUMAR

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G06F12/14

Abstract: Ternary content addressable memory (TCAM) structures and methods of use are disclosed. The memory architecture includes one or more ternary content addressable memory (TCAM) fields, and control logic that applies progressively discriminating data-masking and scores a closeness of a match based on matched and mismatched bits.

公开(公告)号：US20210357138A1

公开(公告)日：2021-11-18

申请号：US15929618

申请日：2020-05-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashish RANJAN ,  Arvind KUMAR ,  Carl RADENS

IPC: G06F3/06 ,  G06N3/04

Abstract: In a deep neural network (DNN), weights are defined that represent a strength of connections between different neurons of the DNN and activations are defined that represent an output produced by a neuron after passing through an activation function of receiving an input and producing an output based on some threshold value. The weight traffic associated with a hybrid memory therefore is distinguished from the activation traffic to the hybrid memory, and one or more data structures may be dynamically allocated in the hybrid memory according to the weights and activations of the or more data structures in the DNN. The hybrid memory includes at least a first memory and a second memory that differ according to write endurance attributes.

公开(公告)号：US20200152270A1

公开(公告)日：2020-05-14

申请号：US16743695

申请日：2020-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor ARSOVSKI ,  Suparna BHATTACHARYA ,  Arvind KUMAR

IPC: G11C15/04 ,  G06F12/14

Abstract: Ternary content addressable memory (TCAM) structures and methods of use are disclosed. The memory architecture includes one or more ternary content addressable memory (TCAM) fields, and control logic that applies progressively discriminating data-masking and scores a closeness of a match based on matched and mismatched bits.

公开(公告)号：US20160204209A1

公开(公告)日：2016-07-14

申请号：US15076021

申请日：2016-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. CHOU ,  Arvind KUMAR ,  Chung-Hsun LIN ,  Shreesh NARASIMHA ,  Claude ORTOLLAND ,  Jonathan T. SHAW

IPC: H01L29/40 ,  H01L21/324 ,  H01L29/66 ,  H01L21/3115

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US20160203985A1

公开(公告)日：2016-07-14

申请号：US15075944

申请日：2016-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. CHOU ,  Arvind KUMAR ,  Chung-Hsun LIN ,  Shreesh NARASIMHA ,  Claude ORTOLLAND ,  Jonathan T. SHAW

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US20180076039A1

公开(公告)日：2018-03-15

申请号：US15813314

申请日：2017-11-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. CHOU ,  Arvind KUMAR ,  Chung-Hsun LIN ,  Shreesh NARASIMHA ,  Claude ORTOLLAND ,  Jonathan T. SHAW

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L29/42368 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28158 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US20160203987A1

公开(公告)日：2016-07-14

申请号：US15076012

申请日：2016-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. CHOU ,  Arvind KUMAR ,  Chung-Hsun LIN ,  Shreesh NARASIMHA ,  Claude ORTOLLAND ,  Jonathan T. SHAW

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US20160149013A1

公开(公告)日：2016-05-26

申请号：US14553521

申请日：2014-11-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. CHOU ,  Arvind KUMAR ,  Chung-Hsun LIN ,  Shreesh NARASIMHA ,  Claude ORTOLLAND ,  Jonathan T. SHAW

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US20170178913A1

公开(公告)日：2017-06-22

申请号：US15450508

申请日：2017-03-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. CHOU ,  Arvind KUMAR ,  Chung-Hsun LIN ,  Shreesh NARASIMHA ,  Claude ORTOLLAND ,  Jonathan T. SHAW

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3115 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US20170040059A1

公开(公告)日：2017-02-09

申请号：US14818764

申请日：2015-08-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor ARSOVSKI ,  Suparna BHATTACHARYA ,  Arvind KUMAR

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: Ternary content addressable memory (TCAM) structures and methods of use are disclosed. The memory architecture includes one or more ternary content addressable memory (TCAM) fields, and control logic that applies progressively discriminating data-masking and scores a closeness of a match based on matched and mismatched bits.

Abstract translation: 公开了三元内容可寻址存储器（TCAM）结构和使用方法。 存储器架构包括一个或多个三元内容可寻址存储器（TCAM）字段，以及控制逻辑，其应用逐行识别数据掩蔽，并且基于匹配和不匹配的比特对匹配的接近进行评分。