Patent search ap:("INTERNATIONAL BUSINESS MACHINES CORPORATION") AND inv:"Chung-Hsun LIN" Page 1

1.

发明申请
ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE 有权

公开(公告)号：US20170178913A1

公开(公告)日：2017-06-22

申请号：US15450508

申请日：2017-03-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. CHOU , Arvind KUMAR , Chung-Hsun LIN , Shreesh NARASIMHA , Claude ORTOLLAND , Jonathan T. SHAW

IPC: H01L21/28 , H01L29/51 , H01L21/02 , H01L29/66 , H01L21/3115 , H01L29/423 , H01L29/78

CPC classification number: H01L21/28158 , H01L21/02181 , H01L21/0223 , H01L21/02247 , H01L21/02255 , H01L21/02323 , H01L21/02332 , H01L21/265 , H01L21/26586 , H01L21/28176 , H01L21/28185 , H01L21/283 , H01L21/3065 , H01L21/3085 , H01L21/31155 , H01L21/324 , H01L21/426 , H01L21/823462 , H01L21/845 , H01L29/401 , H01L29/41791 , H01L29/42356 , H01L29/42368 , H01L29/4238 , H01L29/511 , H01L29/512 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

2.

发明申请
ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE 有权
Title translation: 不对称高K介质，用于减少门诱发漏水泄漏

公开(公告)号：US20160260618A1

公开(公告)日：2016-09-08

申请号：US15159259

申请日：2016-05-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. CHOU , Arvind KUMAR , Chung-Hsun LIN , Shreesh NARASIMHA , Claude ORTOLLAND , Jonathan T. SHAW

IPC: H01L21/3065 , H01L21/283 , H01L21/324 , H01L29/66 , H01L21/308

CPC classification number: H01L21/28158 , H01L21/02181 , H01L21/0223 , H01L21/02247 , H01L21/02255 , H01L21/02323 , H01L21/02332 , H01L21/265 , H01L21/26586 , H01L21/28176 , H01L21/28185 , H01L21/283 , H01L21/3065 , H01L21/3085 , H01L21/31155 , H01L21/324 , H01L21/426 , H01L21/823462 , H01L21/845 , H01L29/401 , H01L29/41791 , H01L29/42356 , H01L29/42368 , H01L29/4238 , H01L29/511 , H01L29/512 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract translation: 公开了一种用于在高k MOSFET中减小栅极感应漏极泄漏的非对称高k电介质和制造方法。该方法包括在栅极结构的高k电介质侧壁上执行注入工艺。该方法还包括进行氧退火处理，以在栅极结构的漏极侧生长氧化物区域，同时抑制邻近源极区域的栅极结构的源极上的氧化物生长。

3.

发明申请
EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT 有权
Title translation: 嵌入式硅锗锗型N型透明效应晶体管，用于降低浮体效应

公开(公告)号：US20140035037A1

公开(公告)日：2014-02-06

申请号：US14049736

申请日：2013-10-09

Applicant: International Business Machines Corporation

Inventor： Leland CHANG , Isaac LAUER , Chung-Hsun LIN , Jeffrey W. SLEIGHT

IPC: H01L27/12

CPC classification number: H01L27/1203 , H01L21/8238 , H01L29/66636 , H01L29/66772 , H01L29/78618 , H01L29/78621

Abstract: A semiconductor device includes a gate stack formed on an active region in a p-type field effect transistor (pFET) portion of a silicon-on-insulator (SOI) substrate. The SOI substrate includes a n-type field effect transistor (nFET) portion. A gate spacer is formed over the gate stack. A source region and a drain region are formed within a first region and a second region, respectively, of the pFET portion of the semiconductor layer including embedded silicon germanium (eSiGe). A source region and a drain region are formed within a first region and a second region, respectively, of the nFET portion of the semiconductor layer including eSiGe. The source and drain regions within the pFET portion includes at least one dimension that is different from at least one dimension of the source and drain regions within the nFET portion.

Abstract translation: 半导体器件包括形成在绝缘体上硅（SOI））衬底的p型场效应晶体管（pFET）部分中的有源区上的栅叠层。 SOI衬底包括n型场效应晶体管（nFET）部分。在栅极堆叠上形成栅极间隔物。源极区域和漏极区域分别形成在包括嵌入硅锗（eSiGe）的半导体层的pFET部分的第一区域和第二区域内。源区域和漏极区域分别形成在包括eSiGe的半导体层的nFET部分的第一区域和第二区域内。 pFET部分内的源极区和漏极区包括与nFET部分内的源极和漏极区的至少一个维度不同的至少一个维度。

4.

发明申请
ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE 有权

公开(公告)号：US20160204209A1

公开(公告)日：2016-07-14

申请号：US15076021

申请日：2016-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. CHOU , Arvind KUMAR , Chung-Hsun LIN , Shreesh NARASIMHA , Claude ORTOLLAND , Jonathan T. SHAW

IPC: H01L29/40 , H01L21/324 , H01L29/66 , H01L21/3115

CPC classification number: H01L21/28158 , H01L21/02181 , H01L21/0223 , H01L21/02247 , H01L21/02255 , H01L21/02323 , H01L21/02332 , H01L21/265 , H01L21/26586 , H01L21/28176 , H01L21/28185 , H01L21/283 , H01L21/3065 , H01L21/3085 , H01L21/31155 , H01L21/324 , H01L21/426 , H01L21/823462 , H01L21/845 , H01L29/401 , H01L29/41791 , H01L29/42356 , H01L29/42368 , H01L29/4238 , H01L29/511 , H01L29/512 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

5.

发明申请
ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE 有权

公开(公告)号：US20160203985A1

公开(公告)日：2016-07-14

申请号：US15075944

申请日：2016-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. CHOU , Arvind KUMAR , Chung-Hsun LIN , Shreesh NARASIMHA , Claude ORTOLLAND , Jonathan T. SHAW

IPC: H01L21/28 , H01L29/51 , H01L29/423

CPC classification number: H01L21/28158 , H01L21/02181 , H01L21/0223 , H01L21/02247 , H01L21/02255 , H01L21/02323 , H01L21/02332 , H01L21/265 , H01L21/26586 , H01L21/28176 , H01L21/28185 , H01L21/283 , H01L21/3065 , H01L21/3085 , H01L21/31155 , H01L21/324 , H01L21/426 , H01L21/823462 , H01L21/845 , H01L29/401 , H01L29/41791 , H01L29/42356 , H01L29/42368 , H01L29/4238 , H01L29/511 , H01L29/512 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

6.

发明申请
EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT 有权
Title translation: 嵌入式硅锗锗型N型透明效应晶体管，用于降低浮体效应

公开(公告)号：US20140038368A1

公开(公告)日：2014-02-06

申请号：US14049765

申请日：2013-10-09

Applicant: International Business Machines Corporation

Inventor： Leland CHANG , Isaac LAUER , Chung-Hsun LIN , Jeffrey W. SLEIGHT

IPC: H01L21/8238

CPC classification number: H01L27/1203 , H01L21/8238 , H01L29/66636 , H01L29/66772 , H01L29/78618 , H01L29/78621

Abstract: A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively.

Abstract translation: 一种用于制造半导体器件的方法包括在绝缘体上硅衬底的有源区上形成栅叠层。有源区在半导体层内并掺杂有p型掺杂剂。围绕栅极堆叠形成栅极间隔物。在为源极区域保留的区域中形成第一沟槽，并且在为漏极区域保留的区域中形成第二沟槽。形成第一和第二沟槽，同时保持暴露为源极区域保留的区域和为漏极区域保留的区域。硅锗外延生长在第一沟槽和第二沟槽内，同时保持分别保留用于源区和漏区的区域。