Invention Application
- Patent Title: BIAS CONFIGURATION FOR WRITE OPERATIONS IN MEMORY
-
Application No.: US15401235Application Date: 2017-01-09
-
Publication No.: US20170117029A1Publication Date: 2017-04-27
- Inventor: Jason Janesky , Syed M. Alam , Dimitri Houssameddine , Mark Deherrera
- Applicant: Everspin Technologies, Inc.
- Main IPC: G11C11/16
- IPC: G11C11/16 ; G11C29/12 ; G11C17/16

Abstract:
Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.
Public/Granted literature
Information query