Invention Application
- Patent Title: TRANSISTOR DEVICE STRUCTURES WITH RETROGRADE WELLS IN CMOS APPLICATIONS
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Application No.: US15792357Application Date: 2017-10-24
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Publication No.: US20180047641A1Publication Date: 2018-02-15
- Inventor: Vara G. Reddy Vakada , Laegu Kang , Michael Ganz , Yi Qi , Puneet Khanna , Srikanth Balaji Samavedam , Sri Charan Vemula , Manfred Eller
- Applicant: GLOBALFOUNDRIES Inc.
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092
Abstract:
A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.
Public/Granted literature
- US10483172B2 Transistor device structures with retrograde wells in CMOS applications Public/Granted day:2019-11-19
Information query
IPC分类:
