The present disclosure relates to an apparatus for training one or more signal timing relations of a control interface between a registering clock driver and one or more data buffers of a memory module comprising a plurality of memory chips, the control interface comprising a clock signal and at least one control signal. The apparatus includes control circuitry which is configured to adjust a relative timing between the at least one control signal and the clock signal based on samples of the at least one control signal sampled based on the clock signal