公开(公告)号：US20220013505A1

公开(公告)日：2022-01-13

申请号：US17485078

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Saravanan Sethuraman ,  Tonia Morris ,  Siaw Kang Lai ,  Yee Choong Lim ,  Yu Ying Ong

IPC: H01L25/065 ,  G11C5/02 ,  G06F12/10

Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

公开(公告)号：US11658159B2

公开(公告)日：2023-05-23

申请号：US17485078

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Saravanan Sethuraman ,  Tonia Morris ,  Siaw Kang Lai ,  Yee Choong Lim ,  Yu Ying Ong

IPC: G11C11/00 ,  H01L25/065 ,  G11C5/02 ,  G06F12/10

CPC classification number: H01L25/0657 ,  G06F12/10 ,  G11C5/025 ,  G06F2212/657 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

公开(公告)号：US11164847B2

公开(公告)日：2021-11-02

申请号：US16701739

申请日：2019-12-03

Applicant: Intel Corporation

Inventor： Saravanan Sethuraman ,  Tonia Morris ,  Siaw Kang Lai ,  Yee Choong Lim ,  Yu Ying Ong

IPC: G11C16/04 ,  H01L25/065 ,  G11C5/02 ,  G06F12/10

Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

公开(公告)号：US20210149707A1

公开(公告)日：2021-05-20

申请号：US17133194

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Akhilesh Thyagaturu ,  Vinodh Gopal ,  Tonia Morris

IPC: G06F9/455 ,  G06F9/38 ,  G06F9/54 ,  G06F16/901

Abstract: Methods, apparatus, systems, and articles of manufacture to process data packets for logical and virtual switch acceleration in memory are disclosed. An example memory includes an input packet buffer to store an inbound data packet from a network; an output packet buffer to store an outbound data packet to transmitted via the network; and programmable logic to: read the inbound data packet from the input packet buffer; process the inbound data packet to determine the outbound data packet; and output the outbound data packet to the output packet buffer.

公开(公告)号：US20190042519A1

公开(公告)日：2019-02-07

申请号：US16023150

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Christina Jue ,  Tonia Morris ,  Zhenglong Wu ,  David Ellis ,  Daniel Becerra

IPC: G06F13/42 ,  G06F3/06

Abstract: A host controller apparatus for determining information related to a time shift for transmitting instructions on a command and address bus includes an interface for transmitting a plurality of instruction signals to a memory module via the command and address bus and for receiving a loopback feedback signal from the memory module. The host controller apparatus further includes a control module configured to transmit the plurality of instruction signals to the memory module via the command and address bus. The control module is configured to receive the loopback feedback signal from the memory module. The loopback feedback signal includes a looped-back composite version of the plurality of instruction signals. The control module is configured to determine the information related to the time shift for transmitting instructions on the command and address bus based on the loopback feedback signal.

公开(公告)号：US20180181504A1

公开(公告)日：2018-06-28

申请号：US15389462

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Tonia Morris ,  John Van Lovelace ,  Christopher Mozak ,  Bill Nale

IPC: G06F13/16 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/4093

CPC classification number: G06F13/1689 ,  G06F12/0238 ,  G06F12/0868 ,  G06F13/1673 ,  G06F2212/7203 ,  G11C5/04 ,  G11C11/4076 ,  G11C11/4093

Abstract: The present disclosure relates to an apparatus for training one or more signal timing relations of a control interface between a registering clock driver and one or more data buffers of a memory module comprising a plurality of memory chips, the control interface comprising a clock signal and at least one control signal. The apparatus includes control circuitry which is configured to adjust a relative timing between the at least one control signal and the clock signal based on samples of the at least one control signal sampled based on the clock signal