公开(公告)号：US20180181504A1

公开(公告)日：2018-06-28

申请号：US15389462

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Tonia Morris ,  John Van Lovelace ,  Christopher Mozak ,  Bill Nale

IPC: G06F13/16 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/4093

CPC classification number: G06F13/1689 ,  G06F12/0238 ,  G06F12/0868 ,  G06F13/1673 ,  G06F2212/7203 ,  G11C5/04 ,  G11C11/4076 ,  G11C11/4093

Abstract: The present disclosure relates to an apparatus for training one or more signal timing relations of a control interface between a registering clock driver and one or more data buffers of a memory module comprising a plurality of memory chips, the control interface comprising a clock signal and at least one control signal. The apparatus includes control circuitry which is configured to adjust a relative timing between the at least one control signal and the clock signal based on samples of the at least one control signal sampled based on the clock signal