Invention Application
- Patent Title: LOW GRANULARITY COARSE DEPTH TEST EFFICIENCY ENHANCEMENT
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Application No.: US16046650Application Date: 2018-07-26
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Publication No.: US20190026855A1Publication Date: 2019-01-24
- Inventor: Vasanth Ranganathan , Saikat Mandal , Karol A. Szerszen , Saurabh Sharma , Vamsee Vardhan Chivukula , Abhishek R. Appu , Joydeep Ray , Prasoonkumar Surti , Altug Koker
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06T1/60
- IPC: G06T1/60 ; G06T1/20 ; G06F12/0875

Abstract:
Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.
Public/Granted literature
- US10748242B2 Low granularity coarse depth test efficiency enhancement Public/Granted day:2020-08-18
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