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公开(公告)号：US20240257433A1
公开(公告)日：2024-08-01
申请号：US18414841
申请日：2024-01-17
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Abhishek R. Appu , Karthik Vaidyanathan , Saikat Mandal , Michael Norris
CPC classification number: G06T15/005 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06T15/06
Abstract: Apparatus and method for asynchronous ray tracing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes including a root node, a plurality of internal nodes, and a plurality of leaf nodes comprising primitives, wherein each internal node comprises a child node to either the root node or another internal node and each leaf node comprises a child node to an internal node; a first storage bank to be arranged as a first plurality of entries; a second storage bank to be arranged as a second plurality of entries, wherein each entry of the first plurality of entries and the second plurality of entries is to store a ray to be traversed through the BVH; an allocator circuit to distribute an incoming ray to either the first storage bank or the second storage bank based on a relative numbers of rays currently stored in the first and second storage banks; and traversal circuitry to alternate between selecting a next ray from the first storage bank and the second storage bank, the traversal circuitry to traverse the next ray through the BVH by reading a next BVH node from a top of a BVH node stack and determining whether the next ray intersects the next BVH node.
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公开(公告)号：US20210035259A1
公开(公告)日：2021-02-04
申请号：US16930935
申请日：2020-07-16
Applicant: Intel Corporation
Inventor： Vasanth Ranganathan , Saikat Mandal , Karol A. Szerszen , Saurabh Sharma , Vamsee Vardhan Chivukula , Abhishek R. Appu , Joydeep Ray , Prasoonkumar Surti , Altug Koker
IPC: G06T1/60 , G06F12/0875 , G06T1/20
Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.
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公开(公告)号：US20200098167A1
公开(公告)日：2020-03-26
申请号：US16456645
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vasanth Ranganathan , Saikat Mandal , Saurabh Sharma , Vamsee Vardhan Chivukula , Karol A. Szerszen , Aleksander Olek Neyman , Altug Koker , Prasoonkumar Surti , Abhishek Appu , Joydeep Ray , Art Hunter , Luis F. Cruz Camacho , Akshay R. Chada
Abstract: Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.
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公开(公告)号：US20190087999A1
公开(公告)日：2019-03-21
申请号：US15710828
申请日：2017-09-20
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Jorge Garcia Pabon , Vasanth Ranganathan , Saikat Mandal , Karol Szerszen , Luis Cruz Camacho , Abhishek R. Appu , Joydeep Ray
CPC classification number: G06T15/005 , G06T1/20 , G06T9/00 , G06T15/40 , G09G5/006 , G09G2360/06 , H04N19/14
Abstract: An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.
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公开(公告)号：US11087522B1
公开(公告)日：2021-08-10
申请号：US16819121
申请日：2020-03-15
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Abhishek R. Appu , Karthik Vaidyanathan , Saikat Mandal , Michael Norris
Abstract: Apparatus and method for asynchronous ray tracing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes including a root node, a plurality of internal nodes, and a plurality of leaf nodes comprising primitives, wherein each internal node comprises a child node to either the root node or another internal node and each leaf node comprises a child node to an internal node; a first storage bank to be arranged as a first plurality of entries; a second storage bank to be arranged as a second plurality of entries, wherein each entry of the first plurality of entries and the second plurality of entries is to store a ray to be traversed through the BVH; an allocator circuit to distribute an incoming ray to either the first storage bank or the second storage bank based on a relative numbers of rays currently stored in the first and second storage banks; and traversal circuitry to alternate between selecting a next ray from the first storage bank and the second storage bank, the traversal circuitry to traverse the next ray through the BVH by reading a next BVH node from a top of a BVH node stack and determining whether the next ray intersects the next BVH node.
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Patent Agency Ranking
公开(公告)号：US11080925B2
公开(公告)日：2021-08-03
申请号：US16456645
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vasanth Ranganathan , Saikat Mandal , Saurabh Sharma , Vamsee Vardhan Chivukula , Karol A. Szerszen , Aleksander Olek Neyman , Altug Koker , Prasoonkumar Surti , Abhishek Appu , Joydeep Ray , Art Hunter , Luis F. Cruz Camacho , Akshay R. Chada
Abstract: Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.
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公开(公告)号：US10430990B2
公开(公告)日：2019-10-01
申请号：US15710828
申请日：2017-09-20
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Jorge Garcia Pabon , Vasanth Ranganathan , Saikat Mandal , Karol Szerszen , Luis Cruz Camacho , Abhishek R. Appu , Joydeep Ray
Abstract: An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.
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公开(公告)号：US12236498B2
公开(公告)日：2025-02-25
申请号：US17332596
申请日：2021-05-27
Applicant: Intel Corporation
Inventor： Saikat Mandal , Karol Szerszen , Vasanth Ranganathan , Altug Koker , Michael Norris , Prasoonkumar Surti , Takahiro Murata
Abstract: Generation and storage of compressed z-planes in graphics processing is described. An example of a processor includes a rasterizer to generate a fragment of pixel data including blocks of pixel data; a depth pipeline to receive the fragment, the pipeline including a first and second depth test hardware, the first depth test hardware to perform a coarse depth test including determining minimum and maximum depths for each block; and a depth buffer, wherein the processor is to determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data and passes a first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane.
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公开(公告)号：US12020370B2
公开(公告)日：2024-06-25
申请号：US18189873
申请日：2023-03-24
Applicant: Intel Corporation
Inventor： Saikat Mandal , Vasanth Ranganathan
CPC classification number: G06T15/405 , G06T1/20 , G06T1/60
Abstract: Embodiments described herein provide for a technique to improve the culling efficiency of coarse depth testing. One embodiment provides for a graphics processor that is configured to perform a method to track a history of source fragments that are tested against a destination tile. When a combination of partial fragments sum to full coverage, the most conservative source far depth value is used instead of the previous destination far depth value. When the combination sums to partial coverage, the previous destination far depth value is retained.
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公开(公告)号：US11900498B2
公开(公告)日：2024-02-13
申请号：US16823741
申请日：2020-03-19
Applicant: Intel Corporation
Inventor： Saikat Mandal , Prasoonkumar Surti , Sven Woop
IPC: G06T1/60 , G06T1/20 , G06T15/00 , G06T17/10 , G06F9/38 , G06F7/24 , G06F7/02 , G06F7/505 , G06T15/08
CPC classification number: G06T1/20 , G06F7/02 , G06F7/24 , G06F7/505 , G06F9/3885 , G06T15/005 , G06T15/08 , G06T17/10
Abstract: Apparatus and method for stable and short latency sorting. For example, one embodiment of a processor comprises: an input circuit to receive a set of N input values to be sorted into a sorted order; comparison circuitry to compare each input value with all other input values in parallel to generate at least N*(N−1)/2 comparison result values; matrix generation circuitry and/or logic to generate a result matrix having a row associated with each input value, a plurality of bits in each row comprising comparison result values indicating results of comparisons with other input values, wherein a first region of the result matrix is to store a first set of bits comprising the N*(N−1)/2 comparison result values and a second region of the result matrix, opposite the first region, is to store a second set of bits comprising an inverse of the N*(N−1)/2 comparison result values; a parallel adder circuit to perform parallel additions of the bits in each row to generate N unique result values; and sorting circuitry to index into the N unique result values to return the sorted order.
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