- 专利标题: PACKAGE SUBSTRATE WITH REDUCED INTERCONNECT STRESS
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申请号: US16541734申请日: 2019-08-15
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公开(公告)号: US20210050306A1公开(公告)日: 2021-02-18
- 发明人: Lauren A. Link , Andrew J. Brown , Sheng C. Li , Sandeep B. Sane
- 申请人: INTEL CORPORATION
- 申请人地址: US CA Santa Clara
- 专利权人: INTEL CORPORATION
- 当前专利权人: INTEL CORPORATION
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H01L23/00
- IPC分类号: H01L23/00 ; H01L23/498 ; H01L23/14 ; H01L23/15
摘要:
Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.
公开/授权文献
- US11824013B2 Package substrate with reduced interconnect stress 公开/授权日:2023-11-21
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