公开(公告)号：US11670504B2

公开(公告)日：2023-06-06

申请号：US16419426

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon C. Marin ,  Andrew J. Brown ,  Dilan Seneviratne

IPC: H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L21/02345 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02194 ,  H01L21/76825 ,  H01L21/76841 ,  H01L23/5329 ,  H01L23/53228 ,  H01L28/60

Abstract: A thin-film insulator comprises a first electrode over a substrate. A photo up-converting material is over the first electrode. A cured photo-imageable dielectric (PID) containing a high-k filler material is over the photo up-converting material, wherein the cured PID is less than 4 μm in thickness, and a second electrode is over the cured PID.

公开(公告)号：US11574874B2

公开(公告)日：2023-02-07

申请号：US16473598

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Robert A. May ,  Sri Ranga Sai Boyapati ,  Kristof Darmawikarta ,  Hiroki Tanaka ,  Srinivas V. Pietambaram ,  Frank Truong ,  Praneeth Akkinepally ,  Andrew J. Brown ,  Lauren A. Link ,  Prithwish Chatterjee

IPC: H01L23/538 ,  H01L21/48

Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.

公开(公告)号：US10692965B2

公开(公告)日：2020-06-23

申请号：US16142817

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Andrew J. Brown ,  Sheng Li ,  Sai Vadlamani ,  Ying Wang

IPC: H01L27/08 ,  H01L49/02 ,  H01F27/28 ,  C09D11/52 ,  H01L23/522 ,  G05F1/625

Abstract: Methods of forming an inductor using dry processes are described. A cavity is laser drilled in an insulator. A first magnetic material layer is printed in the cavity. An Ag conductive ink is printed on the first magnetic material layer and a second magnetic material layer printed on the ink. The ink has a trace sandwiched between the first and second magnetic material layers that provides a majority of the inductance of the inductor. A protective insulating layer protects the second magnetic material layer from a wet chemistry solution when contacts are formed to the ink. The second magnetic material layer and ink are deposited in or on the cavity.

公开(公告)号：US20190333832A1

公开(公告)日：2019-10-31

申请号：US15967122

申请日：2018-04-30

Applicant: Intel Corporation

Inventor： Jonathan Rosch ,  Andrew J. Brown

IPC: H01L23/14 ,  B32B27/12 ,  B32B5/02 ,  B32B5/26 ,  B32B27/38 ,  B32B27/36 ,  H01L23/538 ,  H01L21/48

Abstract: An apparatus is provided which comprises: a woven fiber layer, a first resin layer on a first surface of the woven fiber layer, a second resin layer on a second surface of the woven fiber layer, the second surface opposite the first surface, and the first and the second resin layers comprising cured resin, a third resin layer on the first resin layer, and a fourth resin layer on the second resin layer, the third and the fourth resin layers comprising an uncured resin, and wherein the fourth resin layer has a thickness greater than a thickness of the third resin layer. Other embodiments are also disclosed and claimed.

公开(公告)号：US11862552B2

公开(公告)日：2024-01-02

申请号：US17567639

申请日：2022-01-03

Applicant: INTEL CORPORATION

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Robert A. May ,  Rahul S. Jain ,  Lauren A. Link ,  Andrew J. Brown ,  Kyu Oh Lee ,  Sheng C. Li

IPC: H01L23/498 ,  H01F17/00 ,  H01F41/04 ,  H05K1/00 ,  H01L23/00 ,  H01F27/28 ,  H01F27/40 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/2804 ,  H01F27/40 ,  H01F41/043 ,  H01F41/046 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/19 ,  H01L24/20 ,  H05K1/00 ,  H01F2017/0066 ,  H01F2027/2809 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/16157 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/19042 ,  H01L2924/19102 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.

公开(公告)号：US11610706B2

公开(公告)日：2023-03-21

申请号：US15870302

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Rahul Jain ,  Kyu Oh Lee ,  Sheng C. Li ,  Andrew J. Brown ,  Lauren A. Link

IPC: H01F1/42 ,  H01F27/38 ,  B32B27/38 ,  C22C45/04 ,  H01F17/00 ,  H01L23/498 ,  H01F27/28 ,  H01L21/56 ,  H01F17/06

Abstract: A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.

公开(公告)号：US11251113B2

公开(公告)日：2022-02-15

申请号：US15855453

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Robert A. May ,  Rahul S. Jain ,  Lauren A. Link ,  Andrew J. Brown ,  Kyu Oh Lee ,  Sheng C. Li

IPC: H01L21/48 ,  H01L23/498 ,  H01F17/00 ,  H01F41/04 ,  H05K1/00 ,  H01L23/00 ,  H01F27/28 ,  H01F27/40

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.

公开(公告)号：US11205626B2

公开(公告)日：2021-12-21

申请号：US16875417

申请日：2020-05-15

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Rahul Jain ,  Prithwish Chatterjee ,  Lauren A. Link ,  Sai Vadlamani

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/64 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L21/78

Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

公开(公告)号：US10916486B2

公开(公告)日：2021-02-09

申请号：US16335527

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Chi-Mon Chen ,  Robert Alan May ,  Amanda E. Schuckman ,  Wei-Lun Kane Jen

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/538 ,  H01L21/56 ,  H01L23/367

Abstract: Various embodiments disclosed relate to semiconductor device and method of making the same using functional silanes. In various embodiments, the present invention provides a semiconductor device including a silicon die component having a first silica surface. The semiconductor device includes a dielectric layer having a second surface generally facing the first silica surface. The semiconductor device includes an interface defined between the first surface and the second surface. The semiconductor device also includes a silane based adhesion promoter layer disposed within the junction and bonded to at least one of the first silica surface and the dielectric layer second surface.

公开(公告)号：US20200279819A1

公开(公告)日：2020-09-03

申请号：US16875417

申请日：2020-05-15

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Rahul Jain ,  Prithwish Chatterjee ,  Lauren A. Link ,  Sai Vadlamani

IPC: H01L23/64 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/78

Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.