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    Method to enable 30 microns pitch EMIB or below
    1.
    发明授权
    Method to enable 30 microns pitch EMIB or below 有权

    公开(公告)号：US12230563B2

    公开(公告)日：2025-02-18

    申请号：US17956769

    申请日：2022-09-29

    Applicant: Intel Corporation

    Inventor： Hongxia Feng ,  Dingying David Xu ,  Sheng C. Li ,  Matthew L. Tingey ,  Meizi Jiao ,  Chung Kwang Christopher Tan

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L23/538

    Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

    PACKAGE SUBSTRATE WITH REDUCED INTERCONNECT STRESS
    3.
    发明申请
    PACKAGE SUBSTRATE WITH REDUCED INTERCONNECT STRESS 有权

    公开(公告)号：US20210050306A1

    公开(公告)日：2021-02-18

    申请号：US16541734

    申请日：2019-08-15

    Applicant: INTEL CORPORATION

    Inventor： Lauren A. Link ,  Andrew J. Brown ,  Sheng C. Li ,  Sandeep B. Sane

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L23/15

    Abstract: Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.

    Method to enable 30 microns pitch EMIB or below
    7.
    发明授权
    Method to enable 30 microns pitch EMIB or below 有权

    公开(公告)号：US11088062B2

    公开(公告)日：2021-08-10

    申请号：US15654399

    申请日：2017-07-19

    Applicant: Intel Corporation

    Inventor： Hongxia Feng ,  Dingying David Xu ,  Sheng C. Li ,  Matthew L. Tingey ,  Meizi Jiao ,  Chung Kwang Christopher Tan

    IPC: H01L23/498 ,  H01L23/13 ,  H01L21/48 ,  H01L23/538

    Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

    Sandwich-molded cores for high-inductance architectures
    8.
    发明授权
    Sandwich-molded cores for high-inductance architectures 有权

    公开(公告)号：US11622448B2

    公开(公告)日：2023-04-04

    申请号：US16505403

    申请日：2019-07-08

    Applicant: Intel Corporation

    Inventor： Brandon C. Marin ,  Tarek Ibrahim ,  Srinivas Pietambaram ,  Andrew J. Brown ,  Gang Duan ,  Jeremy Ecton ,  Sheng C. Li

    IPC: H05K1/11 ,  H05K1/16 ,  H01L23/00 ,  H01F27/40 ,  H05K3/40 ,  H05K3/28

    Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.

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