Invention Application
- Patent Title: DOUBLE EDGE TRIGGERED MUX-D SCAN FLIP-FLOP
-
Application No.: US16725689Application Date: 2019-12-23
-
Publication No.: US20210194468A1Publication Date: 2021-06-24
- Inventor: Amit Agarwal , Steven Hsu , Anupama Ambardar Thaploo , Simeon Realov , Ram Krishnamurthy
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H03K3/037
- IPC: H03K3/037 ; H03K3/038 ; G01R31/3177 ; G01R31/317
Abstract:
A family of novel, low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided. The flip-flop takes the advantage of no state node in the slave to remove data inverters in a traditional DET FF to save power, without affecting the flip-flop functionality under coupling/glitch scenarios.
Public/Granted literature
- US11054470B1 Double edge triggered Mux-D scan flip-flop Public/Granted day:2021-07-06
Information query
IPC分类:
