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    High performance fast Mux-D scan flip-flop
    1.
    发明授权
    High performance fast Mux-D scan flip-flop 有权

    公开(公告)号：US11296681B2

    公开(公告)日：2022-04-05

    申请号：US16726020

    申请日：2019-12-23

    申请人： Intel Corporation

    发明人： Amit Agarwal ,  Steven Hsu ,  Simeon Realov ,  Mahesh Kumashikar ,  Ram Krishnamurthy

    IPC分类号： H03K3/00 ,  H03K3/037 ,  G01R31/3177 ,  H03K3/038 ,  H03K19/20

    摘要： A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

    HIGH PERFORMANCE FAST MUX-D SCAN FLIP-FLOP
    3.
    发明申请
    HIGH PERFORMANCE FAST MUX-D SCAN FLIP-FLOP 有权

    公开(公告)号：US20210194469A1

    公开(公告)日：2021-06-24

    申请号：US16726020

    申请日：2019-12-23

    申请人： Intel Corporation

    发明人： Amit Agarwal ,  Steven Hsu ,  Simeon Realov ,  Mahesh Kumashikar ,  Ram Krishnamurthy

    IPC分类号： H03K3/037 ,  H03K19/20 ,  H03K3/038 ,  G01R31/3177

    摘要： A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

    INTEGRATED CLOCK GATE WITH CIRCUITRY TO FACILITATE CLOCK FREQUENCY DIVISION
    5.
    发明公开
    INTEGRATED CLOCK GATE WITH CIRCUITRY TO FACILITATE CLOCK FREQUENCY DIVISION 审中-公开

    公开(公告)号：US20240007087A1

    公开(公告)日：2024-01-04

    申请号：US17856887

    申请日：2022-07-01

    申请人： Intel Corporation

    发明人： Steven Hsu ,  Amit Agarwal ,  Simeon Realov ,  Mark Anders ,  Ram Krishnamurthy

    IPC分类号： H03K3/037 ,  H03K19/21 ,  G06F1/06

    CPC分类号： H03K3/037 ,  H03K19/21 ,  G06F1/06

    摘要： Techniques and mechanisms for an integrated clock gate (ICG) to selectively output a clock signal, and to provide frequency division functionality. In an embodiment, an ICG circuit comprises first circuitry which is coupled to receive a first clock signal, and second circuitry which is coupled to receive a control signal. The first circuitry provides a single edge triggered flip-flop functionality, and is coupled to communicate a feedback signal which the first circuitry is further coupled to receive. Based on the control signal and the feedback signal, the second circuitry performs an exclusive OR (XOR) operation to selectively enable the first circuitry to generate a second clock signal based on the first clock signal. In another embodiment, a frequency of the second clock signal is substantially equal to one half of a frequency of the first clock signal.

    LOW CONTENTION CURRENT CIRCUITS
    9.
    发明公开
    LOW CONTENTION CURRENT CIRCUITS 审中-公开

    公开(公告)号：US20240356552A1

    公开(公告)日：2024-10-24

    申请号：US18305147

    申请日：2023-04-21

    申请人： Intel Corporation

    发明人： Steven Hsu ,  Amit Agarwal ,  Ram Krishnamurthy

    IPC分类号： H03K19/0185 ,  G06F3/06 ,  G11C11/418 ,  G11C11/419 ,  H03K19/21

    CPC分类号： H03K19/018521 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G11C11/418 ,  G11C11/419 ,  H03K19/21

    摘要： A disclosed example includes a read local bitline; and a plurality of pulldown transistor circuits coupled to the read local bitline, a first one of the pulldown transistor circuits including: a first low threshold voltage transistor, the first low threshold voltage transistor including a first drain terminal coupled to the read local bitline; and a second low threshold voltage transistor, the second low threshold voltage transistor including a second drain terminal coupled to a first source terminal of the first low threshold voltage transistor, the second low threshold voltage transistor to persist a voltage level detectable at a gate terminal of the second low threshold voltage transistor, the voltage level representative of a bit of information.

    Configurable Storage Circuits And Methods
    10.
    发明公开
    Configurable Storage Circuits And Methods 审中-公开

    公开(公告)号：US20240337692A1

    公开(公告)日：2024-10-10

    申请号：US18746853

    申请日：2024-06-18

    申请人： Intel Corporation

    发明人： Rajiv Kumar ,  Amit Agarwal ,  Steven Hsu ,  Scott Weber

    IPC分类号： G01R31/3185

    CPC分类号： G01R31/318541 ,  G01R31/318572

    摘要： A flip-flop circuit includes first and second storage circuits. The flip-flop circuit is configurable to store first values of a data signal in the first storage circuit in response to rising edges of a clock signal and to store second values of the data signal in the second storage circuit in response to falling edges of the clock signal during a double edge triggered mode. The flip-flop circuit is configurable to store third values of the data signal in the first storage circuit and to output the third values from the first storage circuit in response to the clock signal during a single edge triggered mode.