Invention Application
- Patent Title: ELECTRONIC DEVICES COMPRISING REDUCED CHARGE CONFINEMENT REGIONS IN STORAGE NODES OF PILLARS AND RELATED METHODS AND SYSTEMS
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Application No.: US17092916Application Date: 2020-11-09
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Publication No.: US20220149068A1Publication Date: 2022-05-12
- Inventor: Yifen Liu , Yan Song , Albert Fayrushin , Naiming Liu , Yingda Dong , George Matamis
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L27/11565 ; H01L27/1157 ; H01L27/11573 ; H01L23/522

Abstract:
An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.
Public/Granted literature
Information query
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