Invention Application
- Patent Title: INTEGRATED CIRCUIT DEVICES HAVING HIGHLY INTEGRATED NMOS AND PMOS TRANSISTORS THEREIN AND METHODS OF FABRICATING THE SAME
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Application No.: US17382956Application Date: 2021-07-22
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Publication No.: US20220165729A1Publication Date: 2022-05-26
- Inventor: Jaehoon Shin , Bongseok Suh , Daewon Kim , Sukhyung Park , Junggun You , Jaeyun Lee
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Priority: KR10-2020-0159293 20201124
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/06 ; H01L29/423 ; H01L29/49 ; H01L29/786 ; H01L21/02 ; H01L21/28 ; H01L21/8238 ; H01L29/66

Abstract:
A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.
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