公开(公告)号：US12229184B2

公开(公告)日：2025-02-18

申请号：US17569914

申请日：2022-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeyun Lee ,  Kyuhong Kim ,  Jiwhan Kim ,  Sungun Park ,  Kiho Cho ,  Jaejoon Han

IPC: G06F16/56 ,  G06F16/55 ,  G06V40/12

Abstract: A processor-implemented method with input data classification includes: extracting an input embedding vector including a feature of biometric information of a user from input data including the biometric information; determining an adaptive embedding vector adaptive to the input embedding vector, based on a combination of a plurality of enrollment embedding vectors that are based on enrollment data; and classifying the input data based on a similarity between the input embedding vector and the adaptive embedding vector.

公开(公告)号：US12299851B2

公开(公告)日：2025-05-13

申请号：US17862568

申请日：2022-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeyun Lee ,  Kyuhong Kim ,  Sungun Park ,  Jaejoon Han

IPC: G06T5/70 ,  G06T5/10 ,  G06V40/12

Abstract: A processor-implemented method with image preprocessing includes: transforming a fingerprint image into a frequency domain; suppressing a low-frequency region corresponding to a first noise component of the fingerprint image in the frequency domain; and restoring the frequency domain, in which the low-frequency region is suppressed, as an image.

公开(公告)号：US20250133819A1

公开(公告)日：2025-04-24

申请号：US19001750

申请日：2024-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehoon Shin ,  Bongseok Suh ,  Daewon Kim ,  Sukhyung Park ,  Junggun You ,  Jaeyun Lee

IPC: H10D84/85 ,  H01L21/02 ,  H01L21/28 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01 ,  H10D64/23 ,  H10D64/27 ,  H10D64/66 ,  H10D84/01 ,  H10D84/03

Abstract: A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.

公开(公告)号：US20240038873A1

公开(公告)日：2024-02-01

申请号：US18483413

申请日：2023-10-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongseok Suh ,  Daewon Kim ,  Beomjin Park ,  Sukhyung Park ,  Sungil Park ,  Jaehoon Shin ,  Bongseob Yang ,  Junggun You ,  Jaeyun Lee

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/78696 ,  H01L29/66553 ,  H01L29/7727

Abstract: A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.

公开(公告)号：US12211847B2

公开(公告)日：2025-01-28

申请号：US17382956

申请日：2021-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehoon Shin ,  Bongseok Suh ,  Daewon Kim ,  Sukhyung Park ,  Junggun You ,  Jaeyun Lee

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.

公开(公告)号：US20240249794A1

公开(公告)日：2024-07-25

申请号：US18394640

申请日：2023-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyun Lee ,  Makoto Hirano ,  Sangsoo Park ,  Jaeduk Yu

IPC: G11C29/52 ,  G11C7/10 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C7/106 ,  G11C29/022

Abstract: A memory device according to an embodiment includes a memory cell array including a plurality of memory cells, a control logic configured to control a verification operation for the plurality of memory cells, a page buffer block including a plurality of page buffers connected to the memory cell array through bit lines, a page buffer decoder that outputs, through an output line. a verification signal generated from at least one of outputs of the plurality of page buffers by a verification operation, and a verification error removal circuit connected to the output line and configured to control an output path of the verification signal to the control logic.

公开(公告)号：US11810964B2

公开(公告)日：2023-11-07

申请号：US17060193

申请日：2020-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongseok Suh ,  Daewon Kim ,  Beomjin Park ,  Sukhyung Park ,  Sungil Park ,  Jaehoon Shin ,  Bongseob Yang ,  Junggun You ,  Jaeyun Lee

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L29/772 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/78696 ,  H01L21/28141 ,  H01L21/823468 ,  H01L29/1037 ,  H01L29/66719 ,  H01L29/7727

Abstract: A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.

公开(公告)号：US20220165729A1

公开(公告)日：2022-05-26

申请号：US17382956

申请日：2021-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehoon Shin ,  Bongseok Suh ,  Daewon Kim ,  Sukhyung Park ,  Junggun You ,  Jaeyun Lee

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.