PAGE BUFFER BLOCK AND MEMORY DEVICE INCLUDING THE SAME

    公开(公告)号:US20240249794A1

    公开(公告)日:2024-07-25

    申请号:US18394640

    申请日:2023-12-22

    CPC classification number: G11C29/52 G11C7/106 G11C29/022

    Abstract: A memory device according to an embodiment includes a memory cell array including a plurality of memory cells, a control logic configured to control a verification operation for the plurality of memory cells, a page buffer block including a plurality of page buffers connected to the memory cell array through bit lines, a page buffer decoder that outputs, through an output line. a verification signal generated from at least one of outputs of the plurality of page buffers by a verification operation, and a verification error removal circuit connected to the output line and configured to control an output path of the verification signal to the control logic.

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