Invention Application
- Patent Title: Dual-sided Routing in 3D SiP Structure
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Application No.: US17690206Application Date: 2022-03-09
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Publication No.: US20220199541A1Publication Date: 2022-06-23
- Inventor: Po-Hao Tsai , Po-Yao Chuang , Meng-Liang Lin , Yi-Wen Wu , Shin-Puu Jeng , Techi Wong
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/48 ; H01L21/56 ; H01L23/00 ; H01L21/768

Abstract:
A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.
Public/Granted literature
- US11824007B2 Dual-sided routing in 3D SiP structure Public/Granted day:2023-11-21
Information query
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