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公开(公告)号：US11380666B2
公开(公告)日：2022-07-05
申请号：US17068026
申请日：2020-10-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Hao Tsai , Techi Wong , Po-Yao Chuang , Shin-Puu Jeng , Meng-Wei Chou , Meng-Liang Lin
Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.
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公开(公告)号：US11239173B2
公开(公告)日：2022-02-01
申请号：US16446796
申请日：2019-06-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Hao Tsai , Meng-Liang Lin , Po-Yao Chuang , Techi Wong , Shin-Puu Jeng
Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a redistribution structure over a carrier substrate and disposing a semiconductor die over the redistribution structure. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across edges of the semiconductor die. The method further includes disposing one or more device elements over the interposer substrate. In addition, the method includes forming a protective layer to surround the semiconductor die.
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公开(公告)号：US20210351118A1
公开(公告)日：2021-11-11
申请号：US17383953
申请日：2021-07-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Hao Tsai , Techi Wong , Meng-Wei Chou , Meng-Liang Lin , Po-Yao Chuang , Shin-Puu Jeng
IPC: H01L23/498 , H01L23/00 , H01L21/48
Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.
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公开(公告)号：US12176337B2
公开(公告)日：2024-12-24
申请号：US17869968
申请日：2022-07-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Wen Wu , Po-Yao Chuang , Meng-Liang Lin , Techi Wong , Shih-Ting Hung , Po-Hao Tsai , Shin-Puu Jeng
Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.
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公开(公告)号：US20240063083A1
公开(公告)日：2024-02-22
申请号：US17891677
申请日：2022-08-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chieh-Lung Lai , Meng-Liang Lin , Hsien-Wei Chen , Shin-Puu Jeng
IPC: H01L23/373 , H01L21/48 , H01L23/00 , H01L23/498
CPC classification number: H01L23/3735 , H01L21/4857 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L24/81 , H01L23/3185 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16238 , H01L2224/81193 , H01L2224/81815 , H01L2924/1517 , H01L2924/3511
Abstract: A semiconductor device includes: a die having die connectors at a front side of the die; a molding material around the die; and a redistribution structure, where the die connectors of the die are attached to a first side of the redistribution structure, where the redistribution structure includes: a dielectric layer; a conductive line extending along a first surface of the dielectric layer facing the die; and a warpage tuning layer contacting and extending along a first surface of the conductive line facing the die, where a first coefficient of thermal expansion (CTE) of the conductive line is smaller than a second CTE of the warpage tuning layer.
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Patent Agency Ranking
公开(公告)号：US11854955B2
公开(公告)日：2023-12-26
申请号：US17383953
申请日：2021-07-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Hao Tsai , Techi Wong , Meng-Wei Chou , Meng-Liang Lin , Po-Yao Chuang , Shin-Puu Jeng
IPC: H01L23/48 , H01L23/498 , H01L23/00 , H01L21/48
CPC classification number: H01L23/49827 , H01L21/486 , H01L24/09 , H01L2224/02379 , H01L2924/3511
Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.
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公开(公告)号：US12300592B2
公开(公告)日：2025-05-13
申请号：US18351809
申请日：2023-07-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Hao Tsai , Techi Wong , Meng-Wei Chou , Meng-Liang Lin , Po-Yao Chuang , Shin-Puu Jeng
IPC: H01L23/48 , H01L21/48 , H01L23/00 , H01L23/498
Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.
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公开(公告)号：US20250079428A1
公开(公告)日：2025-03-06
申请号：US18948727
申请日：2024-11-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Wen Wu , Po-Yao Chuang , Meng-Liang Lin , Techi Wong , Shih-Ting Hung , Po-Hao Tsai , Shin-Puu Jeng
Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.
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公开(公告)号：US11855059B2
公开(公告)日：2023-12-26
申请号：US17808621
申请日：2022-06-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Hao Tsai , Techi Wong , Po-Yao Chuang , Shin-Puu Jeng , Meng-Wei Chou , Meng-Liang Lin
CPC classification number: H01L25/18 , H01L21/566 , H01L23/3114 , H01L23/3128 , H01L24/09 , H01L24/17 , H01L24/32 , H01L24/73 , H01L2224/0231 , H01L2224/02379 , H01L2224/0401
Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.
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公开(公告)号：US11824007B2
公开(公告)日：2023-11-21
申请号：US17690206
申请日：2022-03-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Hao Tsai , Po-Yao Chuang , Meng-Liang Lin , Yi-Wen Wu , Shin-Puu Jeng , Techi Wong
IPC: H01L23/538 , H01L21/48 , H01L21/56 , H01L21/768 , H01L23/00
CPC classification number: H01L23/5384 , H01L21/4885 , H01L21/56 , H01L21/76802 , H01L23/5385 , H01L23/5386 , H01L24/14
Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.
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