Invention Application
- Patent Title: Capping Layers in Metal Gates of Transistors
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Application No.: US17655627Application Date: 2022-03-21
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Publication No.: US20220208984A1Publication Date: 2022-06-30
- Inventor: Tsung-Ta Tang , Yi-Ting Wang , Chung Ta Chen , Hsien-Ming Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L29/49
- IPC: H01L29/49 ; H01L21/02 ; H01L21/28 ; H01L21/285 ; H01L29/08 ; H01L29/40 ; H01L29/66 ; H01L29/78

Abstract:
A method of forming a semiconductor device includes forming a gate electrode in a wafer. The formation of the gate electrode includes depositing a work-function layer, after the work-function layer is deposited, performing a treatment on the wafer, wherein the treatment is performed by soaking the wafer using a silicon-containing gas; after the treatment, forming a metal capping layer over the work-function layer; and depositing a filling metal over the metal capping layer.
Public/Granted literature
- US1747628A Safety-pin holder Public/Granted day:1930-02-18
Information query
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