- 专利标题： DIE-TO-DIE INTERCONNECT
-
申请号： US17852865申请日： 2022-06-29
-
公开(公告)号： US20220342840A1公开(公告)日： 2022-10-27
- 发明人: Debendra Das Sharma , Swadesh Choudhary , Narasimha Lanka , Lakshmipriya Seshan , Gerald Pasdast , Zuoguo Wu
- 申请人： Intel Corporation
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 主分类号： G06F13/42
- IPC分类号： G06F13/42
摘要：
A port is to couple to another die over a die-to-die (D2D) link and includes physical layer (PHY) circuitry including a first number of sideband lanes to carry data for use in training and management of the D2D link, and a second number of mainband lanes to implement a main data path of the D2D link. The mainband lanes include a forwarded clock lane, a valid lane, and a plurality of data lanes. A logical PHY coordinates functions of the sideband lanes and the mainband lanes.
信息查询
