公开(公告)号：US11971841B2

公开(公告)日：2024-04-30

申请号：US17008542

申请日：2020-08-31

申请人： Intel Corporation

发明人： Narasimha Lanka ,  Swadesh Choudhary ,  Mahesh Wagh ,  Lakshmipriya Seshan

IPC分类号： G06F13/42 ,  G06F13/28

CPC分类号： G06F13/4286 ,  G06F13/287 ,  G06F13/4226

摘要： An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.

公开(公告)号：US11818058B2

公开(公告)日：2023-11-14

申请号：US17374545

申请日：2021-07-13

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Swadesh Choudhary

IPC分类号： H04L49/9005 ,  H04L12/40

CPC分类号： H04L49/9005 ,  H04L12/40

摘要： Systems, methods, and computer-readable media are disclosed for an apparatus coupled to a communication bus, where the apparatus includes a queue and a controller to manage operations of the queue. The queue includes a first space to store a first information for a first traffic type, with a first flow class, and for a first virtual channel of communication between a first communicating entity and a second communicating entity. The queue further includes a second space to store a second information for a second traffic type, with a second flow class, and for a second virtual channel of communication between a third communicating entity and a fourth communicating entity. The first traffic type is different from the second traffic type, the first flow class is different from the second flow class, or the first virtual channel is different from the second virtual channel. Other embodiments may be described and/or claimed.

公开(公告)号：US20220342840A1

公开(公告)日：2022-10-27

申请号：US17852865

申请日：2022-06-29

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Swadesh Choudhary ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

IPC分类号： G06F13/42

摘要： A port is to couple to another die over a die-to-die (D2D) link and includes physical layer (PHY) circuitry including a first number of sideband lanes to carry data for use in training and management of the D2D link, and a second number of mainband lanes to implement a main data path of the D2D link. The mainband lanes include a forwarded clock lane, a valid lane, and a plurality of data lanes. A logical PHY coordinates functions of the sideband lanes and the mainband lanes.

公开(公告)号：US20200210315A1

公开(公告)日：2020-07-02

申请号：US16721868

申请日：2019-12-19

申请人： Intel Corporation

发明人： Bahaa Fahim ,  Swadesh Choudhary

IPC分类号： G06F11/34 ,  G06F11/14 ,  G06F11/36

摘要： In one embodiment, a processor comprises a fabric interconnect to couple a first cache agent to at least one of a memory controller or an input/output (I/O) controller; and a first cache agent comprising a cache controller coupled to a cache; and a trace and capture engine to periodically capture a snapshot of state information associated with the first cache agent; trace events to occur at the first cache agent in between captured snapshots; and send the captured snapshots and traced events via the fabric interconnect to the memory controller or I/O controller for storage at a system memory or storage device.

公开(公告)号：US12111783B2

公开(公告)日：2024-10-08

申请号：US18349055

申请日：2023-07-07

申请人： Intel Corporation

发明人： Swadesh Choudhary ,  Robert G. Blankenship ,  Siva Prasad Gadey ,  Sailesh Kumar ,  Vinit Mathew Abraham ,  Yen-Cheng Liu

IPC分类号： G06F13/40

CPC分类号： G06F13/4027

摘要： An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.

公开(公告)号：US20240329129A1

公开(公告)日：2024-10-03

申请号：US18537076

申请日：2023-12-12

申请人： Intel Corporation

发明人： Sridhar Muthrasanallur ,  Debendra Das Sharma ,  Swadesh Choudhary ,  Gerald Pasdast ,  Peter Onufryk

IPC分类号： G01R31/317 ,  G06F11/27 ,  G06F13/42

CPC分类号： G01R31/31705 ,  G06F11/27 ,  G06F13/4221 ,  G06F2213/0026

摘要： Technologies for a unified debug and test architecture in chiplets is disclosed. In an illustrative embodiment, several chiplets are integrated on an integrated circuit package. The chiplets are connected by a package interconnect, such as a universal chiplet interconnect express (UCIe) interconnect. Each chiplet includes several debug nodes, which are connected by an on-chiplet network. One of the chiplets, referred to as a package debug endpoint, acts as a link endpoint for an off-package link, such as a peripheral component interconnect express (PCIe) link. In use, debug messages can be sent to the package debug endpoint over a PCIe link. The debug messages can be routed within the chiplets and between chiplets, allowing for the debug functionality at each debug node to be probed using a common protocol. In this manner, chiplets from different vendors can be integrated into the same package and tested using common software.

公开(公告)号：US20220327084A1

公开(公告)日：2022-10-13

申请号：US17853502

申请日：2022-06-29

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Swadesh Choudhary ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

IPC分类号： G06F13/42 ,  G06F13/40 ,  G06F11/10

摘要： Protocol layer logic in a protocol stack receives an indication that a particular mode is to be utilized on a die-to-die (D2D) link connecting a first device to a second device. The protocol layer logic generates data to be sent on the D2D link to adapt the particular data format to a flit format defined for use on the D2D link in the particular mode, the flit format comprises providing a set of reserved fields to be completed by an adapter block positioned between the protocol circuitry and a physical layer block. The data in the flit format is sent to the data to the adapter block to prepare the data for transmission over the D2D link.

公开(公告)号：US20220308954A1

公开(公告)日：2022-09-29

申请号：US17645828

申请日：2021-12-23

申请人： Intel Corporation

发明人： Swadesh Choudhary ,  Debendra Das Sharma ,  Michelle Jen

IPC分类号： G06F11/07 ,  G06F13/36

摘要： In an embodiment, an apparatus includes a receiver circuit to: in response to a determination that the receiver circuit is in a high latency processing mode, transmit a hint signal to a transmitter circuit; receive a response message from the transmitter circuit; process the response message to reduce a current workload of the receiver circuit; and switch the receiver circuit from the high latency processing mode to a low latency processing mode. Other embodiments are described and claimed.

公开(公告)号：US20210409351A1

公开(公告)日：2021-12-30

申请号：US17374545

申请日：2021-07-13

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Swadesh Choudhary

IPC分类号： H04L12/861 ,  H04L12/40

摘要： Systems, methods, and computer-readable media are disclosed for an apparatus coupled to a communication bus, where the apparatus includes a queue and a controller to manage operations of the queue. The queue includes a first space to store a first information for a first traffic type, with a first flow class, and for a first virtual channel of communication between a first communicating entity and a second communicating entity. The queue further includes a second space to store a second information for a second traffic type, with a second flow class, and for a second virtual channel of communication between a third communicating entity and a fourth communicating entity. The first traffic type is different from the second traffic type, the first flow class is different from the second flow class, or the first virtual channel is different from the second virtual channel. Other embodiments may be described and/or claimed.

公开(公告)号：US11088967B2

公开(公告)日：2021-08-10

申请号：US16525329

申请日：2019-07-29

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Swadesh Choudhary

IPC分类号： H04L12/861 ,  H04L12/40

摘要： Systems, methods, and computer-readable media are disclosed for an apparatus coupled to a communication bus, where the apparatus includes a queue and a controller to manage operations of the queue. The queue includes a first space to store a first information for a first traffic type, with a first flow class, and for a first virtual channel of communication between a first communicating entity and a second communicating entity. The queue further includes a second space to store a second information for a second traffic type, with a second flow class, and for a second virtual channel of communication between a third communicating entity and a fourth communicating entity. The first traffic type is different from the second traffic type, the first flow class is different from the second flow class, or the first virtual channel is different from the second virtual channel. Other embodiments may be described and/or claimed.