Invention Application
- Patent Title: INTEGRATED CIRCUIT WITH NANOSHEET TRANSISTORS WITH ROBUST GATE OXIDE
-
Application No.: US17370822Application Date: 2021-07-08
-
Publication No.: US20230009349A1Publication Date: 2023-01-12
- Inventor: Jia-Ni YU , Kuo-Cheng CHIANG , Mao-Lin HUANG , Lung-Kun CHU , Chung-Wei HSU , Chih-Hao WANG , Kuan-Lun CHENG
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/06 ; H01L29/786 ; H01L29/51 ; H01L21/8234

Abstract:
A method for processing an integrated circuit includes forming I/O gate all around transistors and core gate all around transistors. The method performs a regrowth process on an interfacial gate dielectric layer of the I/O gate all around transistors by diffusing metal atoms into the interfacial dielectric layer I/O gate all around transistor. The regrowth process does not diffuse metal atoms into the interfacial gate dielectric layer of the gate all around core transistor.
Public/Granted literature
- US11869955B2 Integrated circuit with nanosheet transistors with robust gate oxide Public/Granted day:2024-01-09
Information query
IPC分类: