Invention Grant
- Patent Title: Integrated circuit with nanosheet transistors with robust gate oxide
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Application No.: US17370822Application Date: 2021-07-08
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Publication No.: US11869955B2Publication Date: 2024-01-09
- Inventor: Jia-Ni Yu , Kuo-Cheng Chiang , Mao-Lin Huang , Lung-Kun Chu , Chung-Wei Hsu , Chih-Hao Wang , Kuan-Lun Cheng
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Seed IP Law Group LLP
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/06 ; H01L29/786 ; H01L21/8234 ; H01L29/51 ; H01L21/28 ; H01L21/3115 ; H01L27/088

Abstract:
A method for processing an integrated circuit includes forming I/O gate all around transistors and core gate all around transistors. The method performs a regrowth process on an interfacial dielectric layer of the I/O gate all around transistors by diffusing metal atoms into the interfacial dielectric layer of the I/O gate all around transistor. The regrowth process does not diffuse metal atoms into the interfacial gate dielectric layer of the core gate all around transistor.
Public/Granted literature
- US20230009349A1 INTEGRATED CIRCUIT WITH NANOSHEET TRANSISTORS WITH ROBUST GATE OXIDE Public/Granted day:2023-01-12
Information query
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