Invention Publication
- Patent Title: METHOD TO ENHANCE LITHOGRAPHY PATTERN CREATION USING SEMICONDUCTOR STRESS FILM TUNING
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Application No.: US17890766Application Date: 2022-08-18
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Publication No.: US20230251574A1Publication Date: 2023-08-10
- Inventor: Anthony R. SCHEPIS , Daniel J. FULFORD , Mark I. GARDNER , H. Jim FULFORD , Anton J. DEVILLIERS
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Main IPC: G03F7/11
- IPC: G03F7/11 ; G01B11/16 ; G03F7/20

Abstract:
Aspects of the present disclosure provide a method for optimizing wafer shape. For example, the method can include receiving a wafer having a working surface for one or more devices to be fabricated thereon and a backside surface opposite to the working surface, measuring the wafer to identify bow measurement of the wafer, and forming a first stress-modification film on the backside surface. The first stress-modification film can be reactive to a first wavelength of light in that exposure to the first wavelength of light modifies an internal stress of the first stress-modification film. The method can further include exposing the first stress-modification film to a pattern of the first wavelength of light to modify the internal stress of the first stress-modification film. The pattern of the first wavelength of light corresponds to the bow measurement.
Information query
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