公开(公告)号：US20230251574A1

公开(公告)日：2023-08-10

申请号：US17890766

申请日：2022-08-18

Applicant: Tokyo Electron Limited

Inventor： Anthony R. SCHEPIS ,  Daniel J. FULFORD ,  Mark I. GARDNER ,  H. Jim FULFORD ,  Anton J. DEVILLIERS

IPC: G03F7/11 ,  G01B11/16 ,  G03F7/20

CPC classification number: G03F7/11 ,  G01B11/16 ,  G03F7/70783 ,  G03F7/70483

Abstract: Aspects of the present disclosure provide a method for optimizing wafer shape. For example, the method can include receiving a wafer having a working surface for one or more devices to be fabricated thereon and a backside surface opposite to the working surface, measuring the wafer to identify bow measurement of the wafer, and forming a first stress-modification film on the backside surface. The first stress-modification film can be reactive to a first wavelength of light in that exposure to the first wavelength of light modifies an internal stress of the first stress-modification film. The method can further include exposing the first stress-modification film to a pattern of the first wavelength of light to modify the internal stress of the first stress-modification film. The pattern of the first wavelength of light corresponds to the bow measurement.

公开(公告)号：US20230251584A1

公开(公告)日：2023-08-10

申请号：US17889460

申请日：2022-08-17

Applicant: Tokyo Electron Limited

Inventor： Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  H. Jim FULFORD ,  Anton J. DEVILLIERS

IPC: G03F7/20 ,  H01L21/67 ,  H01L21/324 ,  H01L21/66

CPC classification number: G03F7/70783 ,  H01L21/67103 ,  H01L21/67115 ,  H01L21/3247 ,  H01L22/20 ,  H01L21/67288 ,  G03F7/70483

Abstract: Aspects of the present disclosure provide a method for optimizing wafer shape. For example, the method can include receiving a wafer having a working surface for one or more devices to be fabricated thereon and a backside surface opposite to the working surface, measuring the wafer to identify bow measurement of the wafer, and forming a stress-modification film on the backside surface of the wafer. The stress-modification film can be reactive to heat such that applied heat modifies an internal stress of the stress-modification film. The method can also include applying a pattern of heat onto the stress-modification film to modify the internal stress of the stress-modification film, the pattern of heat corresponding to the bow measurement.

公开(公告)号：US20230161267A1

公开(公告)日：2023-05-25

申请号：US17888553

申请日：2022-08-16

Applicant: Tokyo Electron Limited

Inventor： Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  Anton J. DEVILLIERS ,  H. Jim FULFORD

IPC: G03F7/20

CPC classification number: G03F7/70633 ,  G03F7/70625

Abstract: Aspects of the present disclosure provide a method for improving overlay alignment of patterning by correcting wafer shape. For example, the method can include receiving a wafer having a working surface with at least partially-fabricated semiconductor devices, and a backside surface opposite to the working surface. The method can also include forming a first stressor film on the backside surface. The first stressor film can modify overlay alignment of the working surface in a first direction across the working surface of the wafer. The method can also include forming one or more first semiconductor structures on the working surface of the wafer. The first semiconductor structures are aligned in the first direction.

公开(公告)号：US20230359128A1

公开(公告)日：2023-11-09

申请号：US18171989

申请日：2023-02-21

Applicant: Tokyo Electron Limited

Inventor： Andrew WELOTH ,  Michael MURPHY ,  Daniel J. FULFORD ,  Steven GUECI ,  David C. CONKLIN

IPC: G03F7/20

CPC classification number: G03F7/70625 ,  G03F7/70875

Abstract: Aspects of the present disclosure provide a wafer processing device for optimizing wafer shape. For example, the wafer processing device can include a first hot plate, a second hot plate and a controller. The first hot plate can be configured to heat a wafer. For example, the first hot plate can provide uniform heating across a surface of the first hot plate. The second hot plate has multiple heating zones with each heating zone independently controllable such that each heating zone can be set to a temperature value independent of other heating zones. The controller is configured to control the first hot plate to provide the uniform heating, receive a bow measurement from wafer curvature measurement of a wafer, and set the multiple heating zones of the second hot plate to their respective temperature values that correspond to the bow measurement.

公开(公告)号：US20220238328A1

公开(公告)日：2022-07-28

申请号：US17473248

申请日：2021-09-13

Applicant: Tokyo Electron Limited

Inventor： Anton J. DEVILLIERS ,  Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L21/027 ,  H01L23/16

Abstract: Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. For example, the method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof. The method can further include attaching the first side of the first semiconductor structure to a carrier substrate. The method can further include forming a stress film on a second side of the first semiconductor structure. The method can further include separating the carrier substrate from the first semiconductor structure. The method can further include cutting the stress film and the first semiconductor structure to define at least one chiplet. The method can further include bonding the at least one chiplet to a second semiconductor structure having a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

公开(公告)号：US20240201601A1

公开(公告)日：2024-06-20

申请号：US18593330

申请日：2024-03-01

Applicant: Tokyo Electron Limited

Inventor： Andrew WELOTH ,  Michael MURPHY ,  Daniel J. FULFORD ,  Steven GUECI ,  David C. CONKLIN

IPC: G03F7/00

CPC classification number: G03F7/70625 ,  G03F7/70875

Abstract: Aspects of the present disclosure provide a wafer processing device for optimizing wafer shape. For example, the wafer processing device can include a first hot plate, a second hot plate and a controller. The first hot plate can be configured to heat a wafer. For example, the first hot plate can provide uniform heating across a surface of the first hot plate. The second hot plate has multiple heating zones with each heating zone independently controllable such that each heating zone can be set to a temperature value independent of other heating zones. The controller is configured to control the first hot plate to provide the uniform heating, receive a bow measurement from wafer curvature measurement of a wafer, and set the multiple heating zones of the second hot plate to their respective temperature values that correspond to the bow measurement.

公开(公告)号：US20230326738A1

公开(公告)日：2023-10-12

申请号：US17967257

申请日：2022-10-17

Applicant: Tokyo Electron Limited

Inventor： Anthony R. SCHEPIS ,  Daniel J. FULFORD ,  David C. CONKLIN ,  Anton J. DEVILLIERS

IPC: H01L21/02

CPC classification number: H01L21/02118 ,  H01L21/02318

Abstract: Methods described herein address the chuck degradation challenge that can result in wafer distortion upon wafer coupling, leading to downstream fabrication issues. Techniques include actively monitoring wear of a chuck and counteracting chuck degradation by wafer shape manipulation to maintain an ideal working surface. Techniques include using chuck-based flatness metrology and/or modeling based on previous wafer level results and/or historical database of chuck wear information.

公开(公告)号：US20220238380A1

公开(公告)日：2022-07-28

申请号：US17486189

申请日：2021-09-27

Applicant: Tokyo Electron Limited

Inventor： Anton J. DEVILLIERS ,  Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L21/822

Abstract: Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. The method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side to a carrier substrate. The method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure. The method can further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.