公开(公告)号：US20230352343A1

公开(公告)日：2023-11-02

申请号：US18308230

申请日：2023-04-27

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  David POWER ,  Eric Chih-Fang LIU ,  Anton J. DEVILLIERS ,  Kandabara TAPILY ,  Jodi GRZESKOWIAK ,  David CONKLIN ,  Michael MURPHY

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/31144 ,  H01L21/0337 ,  H01L21/76811 ,  H01L23/5226

Abstract: A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.

公开(公告)号：US20230251574A1

公开(公告)日：2023-08-10

申请号：US17890766

申请日：2022-08-18

Applicant: Tokyo Electron Limited

Inventor： Anthony R. SCHEPIS ,  Daniel J. FULFORD ,  Mark I. GARDNER ,  H. Jim FULFORD ,  Anton J. DEVILLIERS

IPC: G03F7/11 ,  G01B11/16 ,  G03F7/20

CPC classification number: G03F7/11 ,  G01B11/16 ,  G03F7/70783 ,  G03F7/70483

Abstract: Aspects of the present disclosure provide a method for optimizing wafer shape. For example, the method can include receiving a wafer having a working surface for one or more devices to be fabricated thereon and a backside surface opposite to the working surface, measuring the wafer to identify bow measurement of the wafer, and forming a first stress-modification film on the backside surface. The first stress-modification film can be reactive to a first wavelength of light in that exposure to the first wavelength of light modifies an internal stress of the first stress-modification film. The method can further include exposing the first stress-modification film to a pattern of the first wavelength of light to modify the internal stress of the first stress-modification film. The pattern of the first wavelength of light corresponds to the bow measurement.

公开(公告)号：US20220351966A1

公开(公告)日：2022-11-03

申请号：US17735707

申请日：2022-05-03

Applicant: Tokyo Electron Limited

Inventor： Anton J. DEVILLIERS

IPC: H01L21/027 ,  H01L21/311

Abstract: A patterning method includes forming a multilayer photoresist stack on a substrate. The multilayer photoresist stack includes a first layer of a wet photoresist, deposited by spin-on deposition, over a second layer of a dry photoresist, deposited by vapor deposition. The multilayer photoresist stack is exposed to a first pattern of actinic radiation including relative, spatially-varying doses of actinic radiation and including high-dose regions, mid-dose regions and low-dose regions. The multilayer photoresist stack and the first pattern of actinic radiation are configured such that after the exposing the multilayer photoresist stack to the first pattern of actinic radiation, in the high-dose regions, developability of both the first layer and the second layer is changed; in the mid-dose regions, developability of the first layer is changed while developability of the second layer is unchanged; in the low-dose regions, developability of both the first layer and the second layer is unchanged.

公开(公告)号：US20190051568A1

公开(公告)日：2019-02-14

申请号：US16164263

申请日：2018-10-18

Applicant: Tokyo Electron Limited

Inventor： Anton J. DEVILLIERS

IPC: H01L21/66 ,  H01J37/32 ,  H01L21/67 ,  H01L21/683 ,  C23C16/46 ,  C23C16/458 ,  C23C16/50 ,  H01L21/3065

Abstract: Techniques herein include systems and methods for fine control of temperature distribution across a substrate. Such techniques can be used to provide uniform spatial temperature distribution, or a biased spatial temperature distribution to improve plasma processing of substrates and/or correct characteristics of a given substrate. Embodiments include a plasma processing system with temperature control. Temperature control systems herein include a primary heating mechanism to heat a substrate, and a secondary heating mechanism that precisely modifies spatial temperature distribution across a substrate being processed. At least one heating mechanism includes a digital projection system configured to project a pattern of electromagnetic radiation onto or into a substrate, or through the substrate and onto a substrate support assembly. The digital projection system is configured to spatially and dynamically adjust the pattern of electromagnetic radiation and selectively augment heating of the substrate by each projected point location.

公开(公告)号：US20230326814A1

公开(公告)日：2023-10-12

申请号：US17885038

申请日：2022-08-10

Applicant: Tokyo Electron Limited

Inventor： Anthony R. SCHEPIS ,  Andrew WELOTH ,  David C. CONKLIN ,  Anton J. DEVILLIERS

IPC: H01L21/66 ,  H01L21/67 ,  H01L21/68 ,  H01L21/02

CPC classification number: H01L22/34 ,  H01L21/67063 ,  H01L21/0226 ,  H01L21/68 ,  H01L21/67098

Abstract: A device includes a first set of modules configured for wafer shape correction and a second set of modules configured for wafer bonding. The first set of modules includes a metrology module configured to measure wafer shape data of a first wafer and a second wafer, including relative z-height values of the first wafer and the second wafer. A stressor film deposition module is configured to form a first stressor film on the first wafer. A stressor film modification module is configured to modify the first stressor film based on a first modification map that defines adjustments to internal stresses of the first wafer and is generated based on the wafer shape data. The second set of modules includes an alignment module configured to align the first wafer with the second wafer, and a bonding module configured to bond the first wafer to the second wafer.

公开(公告)号：US20230251584A1

公开(公告)日：2023-08-10

申请号：US17889460

申请日：2022-08-17

Applicant: Tokyo Electron Limited

Inventor： Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  H. Jim FULFORD ,  Anton J. DEVILLIERS

IPC: G03F7/20 ,  H01L21/67 ,  H01L21/324 ,  H01L21/66

CPC classification number: G03F7/70783 ,  H01L21/67103 ,  H01L21/67115 ,  H01L21/3247 ,  H01L22/20 ,  H01L21/67288 ,  G03F7/70483

Abstract: Aspects of the present disclosure provide a method for optimizing wafer shape. For example, the method can include receiving a wafer having a working surface for one or more devices to be fabricated thereon and a backside surface opposite to the working surface, measuring the wafer to identify bow measurement of the wafer, and forming a stress-modification film on the backside surface of the wafer. The stress-modification film can be reactive to heat such that applied heat modifies an internal stress of the stress-modification film. The method can also include applying a pattern of heat onto the stress-modification film to modify the internal stress of the stress-modification film, the pattern of heat corresponding to the bow measurement.

公开(公告)号：US20210366714A1

公开(公告)日：2021-11-25

申请号：US17325789

申请日：2021-05-20

Applicant: Tokyo Electron Limited

Inventor： Daniel FULFORD ,  Anton J. DEVILLIERS

IPC: H01L21/033 ,  H01L21/027

Abstract: Devices are made by self-aligned quad pitch patterning (SAQP) and methods for making devices by self-aligned quad pitch patterning (SAQP) use a single spacer in the process. An intermediate process step called self-aligned double patterning (SADP) is used to double the pitch following the spacer deposition. A pattern is formed on a substrate, the pattern having ultra-fine resolutions by repeating the SADP step twice for pitch quadrupling and introducing a reversal layer to form a fine trench pattern and hole pattern. An initial pattern is obtained by the X-Y double line exposures. Reverse material is applied on the initial pattern and subsequent etching process converts each initial trench pattern to a line. The pattern designs or pattern layouts have improved LER/LWR (line edge roughness and line width roughness respectively) for below 12 nm lines and trenches in order to create self-aligned cross pitch quad trenches.

公开(公告)号：US20210020435A1

公开(公告)日：2021-01-21

申请号：US16922809

申请日：2020-07-07

Applicant: Tokyo Electron Limited

Inventor： Daniel FULFORD ,  Jodi GRZESKOWIAK ,  Anton J. DEVILLIERS

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/3105

Abstract: The disclosure relates to a method for tuning stress transitions of films on a substrate. The method includes forming a stress-adjustment layer on the substrate, wherein the stress-adjustment layer includes first regions formed of a first material and second regions formed of a second material, wherein the first material includes a first internal stress and the second material includes a second internal stress, and wherein the first internal stress is different compared to the second internal stress; and forming transition regions between the first regions and the second regions, wherein the transition regions include an interface between the first material and the second material that has a predetermined slope that is greater than zero degrees and less than 90 degrees.

公开(公告)号：US20180047832A1

公开(公告)日：2018-02-15

申请号：US15674012

申请日：2017-08-10

Applicant: TOKYO ELECTRON LIMITED

Inventor： Kandabara TAPILY ,  Jeffrey SMITH ,  Nihar MOHANTY ,  Anton J. DEVILLIERS

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

Abstract: A method of forming a semiconductor device having a channel and a source-drain coupled to the channel. The method includes etching a channel region such that an end of the channel region forms a recess within a gate structure surrounding the channel region. An extension region is formed in contact with the channel region and at least partially filling the recess. Extension material of the extension region has a different composition from channel material of the channel region such that a strain is caused in the channel region. A source-drain region is in contact with the extension region and adjacent to the gate structure.

公开(公告)号：US20240042472A1

公开(公告)日：2024-02-08

申请号：US18490409

申请日：2023-10-19

Applicant: Tokyo Electron Limited

Inventor： Mirko VUKOVIC ,  Daniel FULFORD ,  Anton J. DEVILLIERS

IPC: B05B12/08 ,  G01B11/06 ,  H01L21/67

CPC classification number: B05B12/084 ,  G01B11/0625 ,  H01L21/6715 ,  H01L21/67253 ,  G01N2021/556

Abstract: Light can be used to monitor coating a liquid on a substrate. By directing the light to a spot on the substrate, when the liquid passes through the spot, some light will be reflected, while some light will be scattered. Monitoring this behavior can indicate whether a substrate has been successfully coated with the liquid, as well as identifying defects. Further, coating times can be monitored to make process adjustments.